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Added MRegisterInfo hook to re-materialize an instruction.

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llvm-svn: 35205
This commit is contained in:
Evan Cheng 2007-03-20 08:09:38 +00:00
parent b9cc0ade43
commit 41f4f032ee
13 changed files with 106 additions and 16 deletions
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7
include/llvm/Target/MRegisterInfo.h
View File

@ -374,6 +374,13 @@ public:
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const = 0;
/// reMaterialize - Re-issue the specified 'original' instruction at the
/// specific location targeting a new destination register.
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg,
const MachineInstr *Orig) const = 0;
/// foldMemoryOperand - Attempt to fold a load or store of the
/// specified stack slot into the specified machine instruction for
/// the specified operand. If this is possible, a new instruction

51
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -195,6 +195,38 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
abort();
}
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
static void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, int Val,
const TargetInstrInfo &TII, bool isThumb) {
MachineFunction &MF = *MBB.getParent();
MachineConstantPool *ConstantPool = MF.getConstantPool();
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
if (isThumb)
BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
else
BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
.addReg(0).addImm(0);
}
void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
if (Orig->getOpcode() == ARM::MOVi2pieces) {
emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(),
TII, false);
return;
}
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
/// isLowRegister - Returns true if the register is low register r0-r7.
///
static bool isLowRegister(unsigned Reg) {
@ -410,19 +442,6 @@ static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
return NumMIs;
}
/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes
/// immediate.
static void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, int NumBytes,
const TargetInstrInfo &TII) {
MachineFunction &MF = *MBB.getParent();
MachineConstantPool *ConstantPool = MF.getConstantPool();
Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
}
/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
/// in a register using mov / mvn sequences or load the immediate from a
@ -459,7 +478,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, false, false, true);
} else
emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@ -885,7 +904,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
else {
emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
UseRR = true;
}
} else
@ -920,7 +939,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
else {
emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
UseRR = true;
}
} else

3
lib/Target/ARM/ARMRegisterInfo.h
View File

@ -60,6 +60,9 @@ public:
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
int FrameIndex) const;

9
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -155,6 +155,15 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = {
Alpha::R9, Alpha::R10,

3
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -45,6 +45,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;

9
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -93,6 +93,15 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
}
void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = {
IA64::r5, 0

3
lib/Target/IA64/IA64RegisterInfo.h
View File

@ -44,6 +44,9 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;

9
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -239,6 +239,15 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
// 32-bit Darwin calling convention.
static const unsigned Darwin32_CalleeSavedRegs[] = {

3
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -49,6 +49,9 @@ public:
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,

9
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -77,6 +77,15 @@ void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
assert (0 && "Can't copy this register");
}
void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FI) const {

3
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -44,6 +44,9 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FrameIndex) const;

10
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -167,6 +167,16 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
}
void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
MachineInstr *MI = Orig->clone();
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI,
const TargetInstrInfo &TII) {

3
lib/Target/X86/X86RegisterInfo.h
View File

@ -59,6 +59,9 @@ public:
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
/// foldMemoryOperand - If this target supports it, fold a load or store of
/// the specified stack slot into the specified machine instruction for the
/// specified operand. If this is possible, the target should perform the