mirror of
https://github.com/RPCS3/llvm-mirror.git
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added register allocation code
llvm-svn: 585
This commit is contained in:
Ruchira Sasanka
parent
474b31bae5
commit
422a5cb539
@ -5,7 +5,8 @@ LIBRARYNAME = sparc
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Source = \
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Sparc.o \
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Sparc.burm.o \
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SparcInstrSelection.o
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SparcInstrSelection.o \
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SparcRegInfo.o
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include $(LEVEL)/Makefile.common
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@ -14,6 +14,10 @@
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//
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@ -85,6 +89,327 @@ UltraSparcSchedInfo::initializeResources()
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}
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//---------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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// Purpose:
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// This class provides info about sparc register classes.
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//--------------------------------------------------------------------------
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#if 0
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc *const USI ) :
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UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(6)
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{
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
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"6 Float regs are used for float arg passing");
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}
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// ***** TODO insert deletes for reg classes
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UltraSparcRegInfo::~UltraSparcRegInfo(void) { } // empty destructor
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#endif
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//---------------------------------------------------------------------------
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// UltraSparcRegInfo
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// Purpose:
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// This method will color incoming args to a method. If there are more
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// args than that can fit in regs, code will be inserted to pop them from
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// stack
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::colorArgs(const Method *const Meth,
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LiveRangeInfo& LRI) const
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{
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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unsigned intArgNo=0;
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// to keep track of which float regs are allocated for argument passing
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bool FloatArgUsedArr[NumOfFloatArgRegs];
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// init float arg used array
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
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FloatArgUsedArr[i] = false;
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// for each argument
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for( ; ArgIt != ArgList.end() ; ++ArgIt) {
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// get the LR of arg
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LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
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unsigned RegClassID = (LR->getRegClass())->getID();
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// if the arg is in int class - allocate a reg for an int arg
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if( RegClassID == IntRegClassID ) {
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if( intArgNo < NumOfIntArgRegs) {
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LR->setColor( SparcIntRegOrder::i0 + intArgNo );
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if( DEBUG_RA) printReg( LR );
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}
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else {
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// TODO: Insert push code here
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assert( 0 && "Insert push code here!");
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}
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++intArgNo;
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}
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// if the arg is float/double
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else if ( RegClassID == FloatRegClassID) {
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if( LR->getTypeID() == Type::DoubleTyID ) {
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// find the first reg # we can pass a double arg
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for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
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if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
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LR->setColor( SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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FloatArgUsedArr[i+1] = true;
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if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a double");
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}
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}
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else if( LR->getTypeID() == Type::FloatTyID ) {
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// find the first reg # we can pass a float arg
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
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if ( !FloatArgUsedArr[i] ) {
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LR->setColor( SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a float");
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}
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}
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else
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assert(0 && "unknown float type in method arg");
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} // float register class
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else
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assert(0 && "Unknown RegClassID");
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}
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}
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void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
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unsigned RegClassID = (LR->getRegClass())->getID();
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cout << " *Node " << (LR->getUserIGNode())->getIndex();
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if( ! LR->hasColor() ) {
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cout << " - could not find a color" << endl;
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return;
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}
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// if a color is found
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cout << " colored with color "<< LR->getColor();
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if( RegClassID == IntRegClassID ) {
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cout<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
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cout << "]" << endl;
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}
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else if ( RegClassID == FloatRegClassID) {
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cout << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
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if( LR->getTypeID() == Type::DoubleTyID )
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cout << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
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cout << "]" << endl;
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}
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}
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void UltraSparcRegInfo::colorCallArgs(vector<const Instruction *> &
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CallInstrList, LiveRangeInfo& LRI,
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AddedInstrMapType &AddedInstrMap) const
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{
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vector<const Instruction *>::const_iterator InstIt = CallInstrList.begin();
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for( ; InstIt != CallInstrList.end(); ++InstIt) {
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// Inst = LLVM call instruction
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const Instruction *const CallI = *InstIt;
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MachineCodeForVMInstr & MInstVec = CallI->getMachineInstrVec();
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MachineCodeForVMInstr::const_iterator MIIt = MInstVec.begin();
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// find the CALL/JMMPL machine instruction
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for( ; MIIt != MInstVec.end() &&
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! getUltraSparcInfo().getInstrInfo().isCall((*MIIt)->getOpCode());
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++MIIt );
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assert( (MIIt != MInstVec.end()) && "CALL/JMPL not found");
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// CallMI = CALL/JMPL machine isntruction
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const MachineInstr *const CallMI = *MIIt;
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Instruction::op_const_iterator OpIt = CallI->op_begin();
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unsigned intArgNo=0;
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//unsigned NumOfCallInterfs = LR->getNumOfCallInterferences();
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// to keep track of which float regs are allocated for argument passing
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bool FloatArgUsedArr[NumOfFloatArgRegs];
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// init float arg used array
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
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FloatArgUsedArr[i] = false;
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// go thru all the operands of LLVM instruction
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for( ; OpIt != CallI->op_end(); ++OpIt ) {
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// get the LR of call operand (parameter)
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LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *OpIt);
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if ( !LR ) {
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cout << " Warning: In call instr, no LR for arg: " ;
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printValue(*OpIt);
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cout << endl;
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continue;
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}
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unsigned RegClassID = (LR->getRegClass())->getID();
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// if the arg is in int class - allocate a reg for an int arg
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if( RegClassID == IntRegClassID ) {
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if( intArgNo < NumOfIntArgRegs) {
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setCallArgColor( LR, SparcIntRegOrder::o0 + intArgNo );
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}
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else {
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// TODO: Insert push code here
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assert( 0 && "Insert push code here!");
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AddedInstrns * AI = AddedInstrMap[ CallMI ];
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if( ! AI ) AI = new AddedInstrns();
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// AI->InstrnsBefore.push_back( getStackPushInstr(LR) );
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AddedInstrMap[ CallMI ] = AI;
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}
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++intArgNo;
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}
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// if the arg is float/double
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else if ( RegClassID == FloatRegClassID) {
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if( LR->getTypeID() == Type::DoubleTyID ) {
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// find the first reg # we can pass a double arg
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for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
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if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
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setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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FloatArgUsedArr[i+1] = true;
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//if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a double");
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}
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}
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else if( LR->getTypeID() == Type::FloatTyID ) {
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// find the first reg # we can pass a float arg
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
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if ( !FloatArgUsedArr[i] ) {
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setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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// LR->setColor( SparcFloatRegOrder::f0 + i );
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// if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a float");
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}
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}
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else
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assert(0 && "unknown float type in method arg");
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} // float register class
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else
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assert(0 && "Unknown RegClassID");
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} // for each operand in a call instruction
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} // for all call instrctions in CallInstrList
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}
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void UltraSparcRegInfo::setCallArgColor(LiveRange *const LR,
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const unsigned RegNo) const {
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// if no call interference and LR is NOT previously colored (e.g., as an
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// incoming arg)
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if( ! LR->getNumOfCallInterferences() && ! LR->hasColor() ) {
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// we can directly allocate a %o register
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LR->setColor( RegNo);
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if( DEBUG_RA) printReg( LR );
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}
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else { // there are call interferences
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/*
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// insert a copy machine instr to copy from LR to %o(reg)
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PreMInstrMap[ CallMI ] =
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getNewCopyMInstr( LR->, SparcIntRegOrder::o0 + intArgNo );
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*/
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cout << " $$$ TODO: Insert a copy for call argument!: " << endl;
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// We don't color LR here. It's colored as any other normal LR
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}
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}
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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@ -97,13 +422,47 @@ UltraSparcSchedInfo::initializeResources()
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
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InstSchedulingInfo(&InstInfo) {
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InstSchedulingInfo(&InstInfo),
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RegInfo( this ) {
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optSizeForSubWordData = 4;
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minMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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zeroRegNum = 0; // %g0 always gives 0 on Sparc
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}
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//----------------------------------------------------------------------------
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// Entry point for register allocation for a module
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//----------------------------------------------------------------------------
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void AllocateRegisters(Method *M, TargetMachine &TM)
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{
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if ( (M)->isExternal() ) // don't process prototypes
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return;
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if( DEBUG_RA ) {
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cout << endl << "******************** Method "<< (M)->getName();
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cout << " ********************" <<endl;
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}
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MethodLiveVarInfo LVI(M ); // Analyze live varaibles
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LVI.analyze();
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PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
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PRA.allocateRegisters();
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if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
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}
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bool UltraSparc::compileMethod(Method *M) {
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if (SelectInstructionsForMethod(M, *this)) {
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cerr << "Instruction selection failed for method " << M->getName()
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@ -116,6 +475,10 @@ bool UltraSparc::compileMethod(Method *M) {
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<< M->getName() << "\n\n";
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return true;
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}
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AllocateRegisters(M, *this); // allocate registers
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return false;
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}
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@ -853,20 +853,34 @@ public:
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};
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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// class UltraSparcRegInfo
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//
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// Purpose:
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// This class provides info about sparc register classes.
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//---------------------------------------------------------------------------
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class LiveRange;
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class UltraSparc;
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class UltraSparcRegInfo : public MachineRegInfo
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{
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private:
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enum RegClassIDs { IntRegClassID, FloatRegClassID, FloatCCREgClassID };
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enum RegClassIDs {
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IntRegClassID,
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FloatRegClassID,
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IntCCRegClassID,
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FloatCCRegClassID
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};
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// WARNING: If the above enum order must be changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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// reverse pointer to get info about the ultra sparc machine
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const UltraSparc *const UltraSparcInfo;
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@ -883,37 +897,70 @@ class UltraSparcRegInfo : public MachineRegInfo
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public:
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UltraSparcRegInfo(const UltraSparc *USI ) : UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(6)
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{
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UltraSparcRegInfo(const UltraSparc *const USI ) : UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(6)
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{
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
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"6 Float regs are used for float arg passing");
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}
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// ***** TODO Delete
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~UltraSparcRegInfo(void) { } // empty destructor
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inline const UltraSparc & getUltraSparcInfo() const {
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return *UltraSparcInfo;
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}
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inline unsigned getRegClassIDOfValue (const Value *const Val) const {
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inline unsigned getRegClassIDOfValue (const Value *const Val,
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bool isCCReg = false) const {
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Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
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unsigned res;
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if( ty && ty <= Type::LongTyID || (ty == Type::PointerTyID) )
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return IntRegClassID; // sparc int reg (ty=0: void)
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res = IntRegClassID; // sparc int reg (ty=0: void)
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else if( ty <= Type::DoubleTyID)
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return FloatRegClassID; // sparc float reg class
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res = FloatRegClassID; // sparc float reg class
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else {
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cout << "TypeID: " << ty << endl;
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assert(0 && "Cannot resolve register class for type");
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}
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if(isCCReg)
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return res + 2; // corresponidng condition code regiser
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else
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return res;
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}
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#if 0
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unsigned getRCIDOfMachineOp (const MachineOperand & Op) const {
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unsigned Type = getRegClassIDOfValue( Op.getVRegValue() );
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if( Op.getOperandType() == MachineOperand::MO_CCRegister )
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return Type + 2; // because of the order of CC classes
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else return Type;
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}
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#endif
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void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
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|
||||
static void printReg(const LiveRange *const LR) ;
|
||||
@ -929,9 +976,11 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
return reg;
|
||||
else if ( RegClassID == FloatRegClassID && reg < 64)
|
||||
return reg + 32; // we have 32 int regs
|
||||
else if( RegClassID == FloatCCREgClassID && reg < 4)
|
||||
else if( RegClassID == FloatCCRegClassID && reg < 4)
|
||||
return reg + 32 + 64; // 32 int, 64 float
|
||||
else
|
||||
else if( RegClassID == IntCCRegClassID )
|
||||
return 4+ 32 + 64; // only int cc reg
|
||||
else
|
||||
assert(0 && "Invalid register class or reg number");
|
||||
|
||||
}
|
||||
@ -944,8 +993,9 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
else if ( reg < (64 + 32) )
|
||||
return SparcFloatRegOrder::getRegName( reg - 32);
|
||||
else if( reg < (64+32+4) )
|
||||
assert( 0 && "no float condition reg class yet");
|
||||
// return reg + 32 + 64;
|
||||
return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
|
||||
else if ( reg == 64+32+4)
|
||||
return "xcc"; // only integer cc reg
|
||||
else
|
||||
assert(0 && "Invalid register number");
|
||||
}
|
||||
@ -956,9 +1006,6 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
Scheduling guidelines for SPARC IIi:
|
||||
|
||||
@ -1667,12 +1714,15 @@ protected:
|
||||
class UltraSparc : public TargetMachine {
|
||||
UltraSparcInstrInfo InstInfo;
|
||||
UltraSparcSchedInfo InstSchedulingInfo;
|
||||
UltraSparcRegInfo RegInfo;
|
||||
public:
|
||||
UltraSparc();
|
||||
virtual ~UltraSparc() {}
|
||||
|
||||
virtual const MachineInstrInfo& getInstrInfo() const { return InstInfo; }
|
||||
|
||||
virtual const MachineRegInfo& getRegInfo() const { return RegInfo; }
|
||||
|
||||
// compileMethod - For the sparc, we do instruction selection, followed by
|
||||
// delay slot scheduling, then register allocation.
|
||||
//
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
#include "llvm/CodeGen/IGNode.h"
|
||||
#include "SparcRegInfo.h"
|
||||
#include "SparcInternals.h"
|
||||
|
||||
#include "llvm/Target/Sparc.h"
|
||||
|
||||
|
||||
@ -4,17 +4,20 @@
|
||||
Purpose: Contains the description of integer register class of Sparc
|
||||
*/
|
||||
|
||||
#ifndef SPARC_INT_REG_CLASS_H
|
||||
#define SPARC_INT_REG_CLASS_H
|
||||
|
||||
#ifndef SPARC_REG_INFO_CLASS_H
|
||||
#define SPARC_REG_INFO_CLASS_H
|
||||
|
||||
#include "llvm/Target/RegInfo.h"
|
||||
#include "llvm/CodeGen/IGNode.h"
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Integer Register Class
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
// Int register names in same order as enum in class SparcIntRegOrder
|
||||
//
|
||||
|
||||
static string const IntRegNames[] =
|
||||
{ "g1", "g2", "g3", "g4", "g5", "g6", "g7",
|
||||
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
|
||||
@ -80,7 +83,7 @@ class SparcIntRegClass : public MachineRegClassInfo
|
||||
public:
|
||||
|
||||
SparcIntRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(0,
|
||||
: MachineRegClassInfo(ID,
|
||||
SparcIntRegOrder::NumOfAvailRegs,
|
||||
SparcIntRegOrder::NumOfAllRegs)
|
||||
{ }
|
||||
@ -141,6 +144,7 @@ class SparcFloatRegOrder{
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcFloatRegClass : public MachineRegClassInfo
|
||||
{
|
||||
private:
|
||||
@ -151,7 +155,7 @@ class SparcFloatRegClass : public MachineRegClassInfo
|
||||
public:
|
||||
|
||||
SparcFloatRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(1,
|
||||
: MachineRegClassInfo(ID,
|
||||
SparcFloatRegOrder::NumOfAvailRegs,
|
||||
SparcFloatRegOrder::NumOfAllRegs)
|
||||
{ }
|
||||
@ -162,4 +166,75 @@ class SparcFloatRegClass : public MachineRegClassInfo
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Int CC Register Class
|
||||
// Only one integer cc register is available
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
class SparcIntCCRegClass : public MachineRegClassInfo
|
||||
{
|
||||
public:
|
||||
|
||||
SparcIntCCRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID,1, 1) { }
|
||||
|
||||
inline void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
|
||||
Node->setColor(0); // only one int cc reg is available
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Float CC Register Class
|
||||
// Only 4 Float CC registers are available
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
static string const FloatCCRegNames[] =
|
||||
{
|
||||
"fcc0", "fcc1", "fcc2", "fcc3"
|
||||
};
|
||||
|
||||
|
||||
class SparcFloatCCRegOrder{
|
||||
|
||||
public:
|
||||
|
||||
enum RegsInPrefOrder {
|
||||
|
||||
fcc0, fcc1, fcc2, fcc3
|
||||
};
|
||||
|
||||
static const string getRegName(const unsigned reg) {
|
||||
assert( reg < 4 );
|
||||
return FloatCCRegNames[reg];
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcFloatCCRegClass : public MachineRegClassInfo
|
||||
{
|
||||
public:
|
||||
|
||||
SparcFloatCCRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID, 4, 4) { }
|
||||
|
||||
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
|
||||
int c;
|
||||
for(c=0; c < 4 && IsColorUsedArr[c] ; ++c) ; // find color
|
||||
assert( (c < 4) && "Can allocate only 4 float cc registers");
|
||||
Node->setColor(c);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user