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Eliminated the classification of control registers into %ecr_

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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
This commit is contained in:
Sean Callanan 2010-05-06 20:59:00 +00:00
parent 33433c1e3c
commit 4331428e24
10 changed files with 38 additions and 70 deletions
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3
lib/Target/X86/Disassembler/X86Disassembler.cpp
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@ -420,8 +420,7 @@ static bool translateRM(MCInst &mcInst,
case TYPE_XMM64:
case TYPE_XMM128:
case TYPE_DEBUGREG:
case TYPE_CR32:
case TYPE_CR64:
case TYPE_CONTROLREG:
return translateRMRegister(mcInst, insn);
case TYPE_M:
case TYPE_M8:

8
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
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@ -1034,14 +1034,10 @@ static int readModRM(struct InternalInstruction* insn) {
if (index > 7) \
*valid = 0; \
return prefix##_DR0 + index; \
case TYPE_CR32: \
if (index > 7) \
*valid = 0; \
return prefix##_ECR0 + index; \
case TYPE_CR64: \
case TYPE_CONTROLREG: \
if (index > 8) \
*valid = 0; \
return prefix##_RCR0 + index; \
return prefix##_CR0 + index; \
} \
}

33
lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
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@ -225,26 +225,16 @@ extern "C" {
ENTRY(DR6) \
ENTRY(DR7)
#define REGS_CONTROL_32BIT \
ENTRY(ECR0) \
ENTRY(ECR1) \
ENTRY(ECR2) \
ENTRY(ECR3) \
ENTRY(ECR4) \
ENTRY(ECR5) \
ENTRY(ECR6) \
ENTRY(ECR7)
#define REGS_CONTROL_64BIT \
ENTRY(RCR0) \
ENTRY(RCR1) \
ENTRY(RCR2) \
ENTRY(RCR3) \
ENTRY(RCR4) \
ENTRY(RCR5) \
ENTRY(RCR6) \
ENTRY(RCR7) \
ENTRY(RCR8)
#define REGS_CONTROL \
ENTRY(CR0) \
ENTRY(CR1) \
ENTRY(CR2) \
ENTRY(CR3) \
ENTRY(CR4) \
ENTRY(CR5) \
ENTRY(CR6) \
ENTRY(CR7) \
ENTRY(CR8)
#define ALL_EA_BASES \
EA_BASES_16BIT \
@ -264,8 +254,7 @@ extern "C" {
REGS_XMM \
REGS_SEGMENT \
REGS_DEBUG \
REGS_CONTROL_32BIT \
REGS_CONTROL_64BIT \
REGS_CONTROL \
ENTRY(RIP)
/*

3
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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@ -280,8 +280,7 @@ struct ContextDecision {
ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CR32, "4-byte control register operand") \
ENUM_ENTRY(TYPE_CR64, "8-byte") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
\
ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \

4
lib/Target/X86/X86Instr64bit.td
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@ -398,9 +398,9 @@ def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
// Moves to and from control registers
def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
// Sign/Zero extenders

8
lib/Target/X86/X86InstrInfo.td
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@ -1059,10 +1059,10 @@ def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
// Moves to and from control registers
def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...

37
lib/Target/X86/X86RegisterInfo.td
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@ -207,24 +207,15 @@ let Namespace = "X86" in {
def DR7 : Register<"dr7">;
// Condition registers
def ECR0 : Register<"ecr0">;
def ECR1 : Register<"ecr1">;
def ECR2 : Register<"ecr2">;
def ECR3 : Register<"ecr3">;
def ECR4 : Register<"ecr4">;
def ECR5 : Register<"ecr5">;
def ECR6 : Register<"ecr6">;
def ECR7 : Register<"ecr7">;
def RCR0 : Register<"rcr0">;
def RCR1 : Register<"rcr1">;
def RCR2 : Register<"rcr2">;
def RCR3 : Register<"rcr3">;
def RCR4 : Register<"rcr4">;
def RCR5 : Register<"rcr5">;
def RCR6 : Register<"rcr6">;
def RCR7 : Register<"rcr7">;
def RCR8 : Register<"rcr8">;
def CR0 : Register<"cr0">;
def CR1 : Register<"cr1">;
def CR2 : Register<"cr2">;
def CR3 : Register<"cr3">;
def CR4 : Register<"cr4">;
def CR5 : Register<"cr5">;
def CR6 : Register<"cr6">;
def CR7 : Register<"cr7">;
def CR8 : Register<"cr8">;
}
@ -511,14 +502,8 @@ def DEBUG_REG : RegisterClass<"X86", [i32], 32,
}
// Control registers.
def CONTROL_REG_32 : RegisterClass<"X86", [i32], 32,
[ECR0, ECR1, ECR2, ECR3, ECR4, ECR5, ECR6,
ECR7]> {
}
def CONTROL_REG_64 : RegisterClass<"X86", [i64], 64,
[RCR0, RCR1, RCR2, RCR3, RCR4, RCR5, RCR6,
RCR7, RCR8]> {
def CONTROL_REG : RegisterClass<"X86", [i64], 64,
[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
}
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of

3
test/MC/Disassembler/simple-tests.txt
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@ -54,3 +54,6 @@
# CHECK: movl $0, -4(%rbp)
0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
# CHECK: movq %cr0, %rcx
0x0f 0x20 0xc1

3
utils/TableGen/EDEmitter.cpp
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@ -309,8 +309,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type,
REG("RST");
REG("SEGMENT_REG");
REG("DEBUG_REG");
REG("CONTROL_REG_32");
REG("CONTROL_REG_64");
REG("CONTROL_REG");
IMM("i8imm");
IMM("i16imm");

6
utils/TableGen/X86RecognizableInstr.cpp
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@ -835,8 +835,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("opaque512mem", TYPE_M512)
TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
TYPE("DEBUG_REG", TYPE_DEBUGREG)
TYPE("CONTROL_REG_32", TYPE_CR32)
TYPE("CONTROL_REG_64", TYPE_CR64)
TYPE("CONTROL_REG", TYPE_CONTROLREG)
TYPE("offset8", TYPE_MOFFS8)
TYPE("offset16", TYPE_MOFFS16)
TYPE("offset32", TYPE_MOFFS32)
@ -895,8 +894,7 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString
ENCODING("VR64", ENCODING_REG)
ENCODING("SEGMENT_REG", ENCODING_REG)
ENCODING("DEBUG_REG", ENCODING_REG)
ENCODING("CONTROL_REG_32", ENCODING_REG)
ENCODING("CONTROL_REG_64", ENCODING_REG)
ENCODING("CONTROL_REG", ENCODING_REG)
errs() << "Unhandled reg/opcode register encoding " << s << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding");
}