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Test cases for SSSE3/AVX integer horizontal add/sub.
llvm-svn: 144990
This commit is contained in:
Craig Topper
parent
a64e2604a2
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44b06b0096
170
test/CodeGen/X86/phaddsub.ll
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170
test/CodeGen/X86/phaddsub.ll
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; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
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; SSSE3: phaddw1:
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; SSSE3-NOT: vphaddw
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; SSSE3: phaddw
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; AVX: phaddw1:
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; AVX: vphaddw
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define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%r = add <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3: phaddw2:
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; SSSE3-NOT: vphaddw
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; SSSE3: phaddw
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; AVX: phaddw2:
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; AVX: vphaddw
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define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
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%b = shufflevector <8 x i16> %y, <8 x i16> %x, <8 x i32> <i32 8, i32 11, i32 12, i32 15, i32 0, i32 3, i32 4, i32 7>
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%r = add <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3: phaddd1:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd1:
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; AVX: vphaddd
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define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd2:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd2:
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; AVX: vphaddd
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define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
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%b = shufflevector <4 x i32> %y, <4 x i32> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd3:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd3:
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; AVX: vphaddd
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define <4 x i32> @phaddd3(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd4:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd4:
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; AVX: vphaddd
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define <4 x i32> @phaddd4(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd5:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd5:
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; AVX: vphaddd
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define <4 x i32> @phaddd5(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd6:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd6:
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; AVX: vphaddd
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define <4 x i32> @phaddd6(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phaddd7:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX: phaddd7:
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; AVX: vphaddd
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define <4 x i32> @phaddd7(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phsubw1:
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; SSSE3-NOT: vphsubw
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; SSSE3: phsubw
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; AVX: phsubw1:
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; AVX: vphsubw
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define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%r = sub <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3: phsubd1:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX: phsubd1:
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; AVX: vphsubd
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define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phsubd2:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX: phsubd2:
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; AVX: vphsubd
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define <4 x i32> @phsubd2(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phsubd3:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX: phsubd3:
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; AVX: vphsubd
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define <4 x i32> @phsubd3(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3: phsubd4:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX: phsubd4:
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; AVX: vphsubd
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define <4 x i32> @phsubd4(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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