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Enable Mips16 compiler to compile a null program.

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First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408
This commit is contained in:
Akira Hatanaka 2012-05-24 18:32:33 +00:00
parent 93e40b754a
commit 44ebe6c79d
5 changed files with 39 additions and 6 deletions
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4
lib/Target/Mips/Mips16InstrFormats.td
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@ -173,7 +173,7 @@ class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
//===----------------------------------------------------------------------===//
class FRR16<bits<5> op, bits<5> _funct, dag outs, dag ins, string asmstr,
class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
{
@ -181,7 +181,7 @@ class FRR16<bits<5> op, bits<5> _funct, dag outs, dag ins, string asmstr,
bits<3> ry;
bits<5> funct;
let Opcode = op;
let Opcode = 0b11101;
let funct = _funct;
let Inst{10-8} = rx;

18
lib/Target/Mips/Mips16InstrInfo.td Normal file
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@ -0,0 +1,18 @@
//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes Mips16 instructions.
//
//===----------------------------------------------------------------------===//
let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
isBarrier=1, hasCtrlDep=1, rx=0b000, ry=0b001 in
def RET16 : FRR16 <0, (outs), (ins CPURAReg:$target),
"jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>,
Requires<[InMips16Mode]>;

11
lib/Target/Mips/MipsInstrInfo.td
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@ -140,6 +140,8 @@ def IsN64 : Predicate<"Subtarget.isABI_N64()">,
AssemblerPredicate<"FeatureN64">;
def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
AssemblerPredicate<"!FeatureN64">;
def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">;
def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
AssemblerPredicate<"FeatureMips32">;
def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
@ -147,8 +149,8 @@ def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
AssemblerPredicate<"FeatureMips32">;
def HasStandardEncoding:
Predicate<"Subtarget.hasStandardEncoding()">,
AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
Predicate<"Subtarget.hasStandardEncoding()">,
AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
//===----------------------------------------------------------------------===//
// Instruction format superclass
@ -256,7 +258,8 @@ def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
// Mips Address Mode! SDNode frameindex could possibily be a match
// since load and store instructions from stack used it.
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
def addr :
ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
//===----------------------------------------------------------------------===//
// Pattern fragment for load/store
@ -1211,4 +1214,4 @@ include "MipsCondMov.td"
// Mips16
include "Mips16InstrFormats.td"
include "Mips16InstrInfo.td"

2
lib/Target/Mips/MipsRegisterInfo.td
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@ -271,6 +271,8 @@ def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Callee save
S0, S1)>;
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>;
// 64bit fp:
// * FGR64 - 32 64-bit registers

10
test/CodeGen/Mips/null.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
define i32 @main() nounwind {
entry:
ret i32 0
; 16: jr $ra
}