mirror of
https://github.com/RPCS3/llvm-mirror.git
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remove JIT support from the Alpha backend. The JIT will be moving to MC,
and the Alpha backend isn't MCized yet. Approved by Andrew. llvm-svn: 119051
This commit is contained in:
Chris Lattner
parent
05a7c613fa
commit
4533444a49
@ -388,9 +388,7 @@ ifeq ($(ENABLE_PIC),0)
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CXX.Flags += -fPIC
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CPP.BaseFlags += -fPIC
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endif
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endif
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ifeq ($(ARCH),Alpha)
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LD.Flags += -Wl,--no-relax
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endif
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@ -480,7 +480,7 @@ else
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Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
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PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
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x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
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Alpha) AC_SUBST(TARGET_HAS_JIT,1) ;;
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Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
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ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
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Mips) AC_SUBST(TARGET_HAS_JIT,0) ;;
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XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
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2
configure
vendored
2
configure
vendored
@ -4850,7 +4850,7 @@ else
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;;
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x86_64) TARGET_HAS_JIT=1
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;;
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Alpha) TARGET_HAS_JIT=1
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Alpha) TARGET_HAS_JIT=0
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;;
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ARM) TARGET_HAS_JIT=1
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;;
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@ -1,222 +0,0 @@
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//===-- Alpha/AlphaCodeEmitter.cpp - Convert Alpha code to machine code ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the Alpha machine instructions
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// into relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "alpha-emitter"
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#include "AlphaTargetMachine.h"
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#include "AlphaRelocations.h"
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#include "Alpha.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class AlphaCodeEmitter : public MachineFunctionPass {
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JITCodeEmitter &MCE;
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const AlphaInstrInfo *II;
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public:
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static char ID;
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AlphaCodeEmitter(JITCodeEmitter &mce) : MachineFunctionPass(ID),
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MCE(mce) {}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
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/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Alpha Machine Code Emitter";
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}
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private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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};
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}
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char AlphaCodeEmitter::ID = 0;
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/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha
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/// code to the specified MCE object.
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FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM,
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JITCodeEmitter &JCE) {
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return new AlphaCodeEmitter(JCE);
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}
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bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
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do {
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MCE.startFunction(MF);
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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emitBasicBlock(*I);
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} while (MCE.finishFunction(MF));
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return false;
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}
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void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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MCE.StartMachineBasicBlock(&MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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const MachineInstr &MI = *I;
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MCE.processDebugLoc(MI.getDebugLoc(), true);
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switch(MI.getOpcode()) {
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default:
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MCE.emitWordLE(getBinaryCodeForInstr(*I));
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break;
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case Alpha::ALTENT:
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case Alpha::PCLABEL:
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case Alpha::MEMLABEL:
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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break; //skip these
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}
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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}
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}
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static unsigned getAlphaRegNumber(unsigned Reg) {
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switch (Reg) {
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case Alpha::R0 : case Alpha::F0 : return 0;
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case Alpha::R1 : case Alpha::F1 : return 1;
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case Alpha::R2 : case Alpha::F2 : return 2;
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case Alpha::R3 : case Alpha::F3 : return 3;
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case Alpha::R4 : case Alpha::F4 : return 4;
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case Alpha::R5 : case Alpha::F5 : return 5;
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case Alpha::R6 : case Alpha::F6 : return 6;
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case Alpha::R7 : case Alpha::F7 : return 7;
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case Alpha::R8 : case Alpha::F8 : return 8;
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case Alpha::R9 : case Alpha::F9 : return 9;
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case Alpha::R10 : case Alpha::F10 : return 10;
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case Alpha::R11 : case Alpha::F11 : return 11;
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case Alpha::R12 : case Alpha::F12 : return 12;
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case Alpha::R13 : case Alpha::F13 : return 13;
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case Alpha::R14 : case Alpha::F14 : return 14;
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case Alpha::R15 : case Alpha::F15 : return 15;
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case Alpha::R16 : case Alpha::F16 : return 16;
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case Alpha::R17 : case Alpha::F17 : return 17;
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case Alpha::R18 : case Alpha::F18 : return 18;
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case Alpha::R19 : case Alpha::F19 : return 19;
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case Alpha::R20 : case Alpha::F20 : return 20;
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case Alpha::R21 : case Alpha::F21 : return 21;
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case Alpha::R22 : case Alpha::F22 : return 22;
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case Alpha::R23 : case Alpha::F23 : return 23;
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case Alpha::R24 : case Alpha::F24 : return 24;
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case Alpha::R25 : case Alpha::F25 : return 25;
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case Alpha::R26 : case Alpha::F26 : return 26;
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case Alpha::R27 : case Alpha::F27 : return 27;
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case Alpha::R28 : case Alpha::F28 : return 28;
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case Alpha::R29 : case Alpha::F29 : return 29;
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case Alpha::R30 : case Alpha::F30 : return 30;
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case Alpha::R31 : case Alpha::F31 : return 31;
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default:
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llvm_unreachable("Unhandled reg");
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}
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}
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unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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if (MO.isReg()) {
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rv = getAlphaRegNumber(MO.getReg());
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} else if (MO.isImm()) {
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rv = MO.getImm();
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} else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
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DEBUG(errs() << MO << " is a relocated op for " << MI << "\n");
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unsigned Reloc = 0;
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int Offset = 0;
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bool useGOT = false;
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switch (MI.getOpcode()) {
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case Alpha::BSR:
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Reloc = Alpha::reloc_bsr;
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break;
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case Alpha::LDLr:
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case Alpha::LDQr:
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case Alpha::LDBUr:
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case Alpha::LDWUr:
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case Alpha::LDSr:
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case Alpha::LDTr:
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case Alpha::LDAr:
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case Alpha::STQr:
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case Alpha::STLr:
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case Alpha::STWr:
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case Alpha::STBr:
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case Alpha::STSr:
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case Alpha::STTr:
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Reloc = Alpha::reloc_gprellow;
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break;
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case Alpha::LDAHr:
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Reloc = Alpha::reloc_gprelhigh;
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break;
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case Alpha::LDQl:
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Reloc = Alpha::reloc_literal;
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useGOT = true;
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break;
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case Alpha::LDAg:
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case Alpha::LDAHg:
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Reloc = Alpha::reloc_gpdist;
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Offset = MI.getOperand(3).getImm();
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break;
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default:
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llvm_unreachable("unknown relocatable instruction");
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}
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if (MO.isGlobal())
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MCE.addRelocation(MachineRelocation::getGV(
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MCE.getCurrentPCOffset(),
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Reloc,
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const_cast<GlobalValue *>(MO.getGlobal()),
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Offset,
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isa<Function>(MO.getGlobal()),
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useGOT));
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else if (MO.isSymbol())
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, MO.getSymbolName(),
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Offset, true));
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else
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, MO.getIndex(), Offset));
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} else if (MO.isMBB()) {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Alpha::reloc_bsr, MO.getMBB()));
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} else {
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#ifndef NDEBUG
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errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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#endif
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llvm_unreachable(0);
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}
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return rv;
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}
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#include "AlphaGenCodeEmitter.inc"
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@ -1,310 +0,0 @@
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//===-- AlphaJITInfo.cpp - Implement the JIT interfaces for the Alpha ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the JIT interfaces for the Alpha target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "AlphaJITInfo.h"
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#include "AlphaRelocations.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdlib>
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using namespace llvm;
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#define BUILD_OFormatI(Op, RA, LIT, FUN, RC) \
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((Op << 26) | (RA << 21) | (LIT << 13) | (1 << 12) | (FUN << 5) | (RC))
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#define BUILD_OFormat(Op, RA, RB, FUN, RC) \
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((Op << 26) | (RA << 21) | (RB << 16) | (FUN << 5) | (RC))
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#define BUILD_LDA(RD, RS, IMM16) \
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((0x08 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
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#define BUILD_LDAH(RD, RS, IMM16) \
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((0x09 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
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#define BUILD_LDQ(RD, RS, IMM16) \
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((0x29 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF))
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#define BUILD_JMP(RD, RS, IMM16) \
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((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x00 << 14) | ((IMM16) & 0x3FFF))
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#define BUILD_JSR(RD, RS, IMM16) \
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((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x01 << 14) | ((IMM16) & 0x3FFF))
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#define BUILD_SLLi(RD, RS, IMM8) \
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(BUILD_OFormatI(0x12, RS, IMM8, 0x39, RD))
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#define BUILD_ORi(RD, RS, IMM8) \
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(BUILD_OFormatI(0x11, RS, IMM8, 0x20, RD))
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#define BUILD_OR(RD, RS, RT) \
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(BUILD_OFormat(0x11, RS, RT, 0x20, RD))
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static void EmitBranchToAt(void *At, void *To) {
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unsigned long Fn = (unsigned long)To;
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unsigned *AtI = (unsigned*)At;
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AtI[0] = BUILD_OR(0, 27, 27);
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DEBUG(errs() << "Stub targeting " << To << "\n");
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for (int x = 1; x <= 8; ++x) {
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AtI[2*x - 1] = BUILD_SLLi(27,27,8);
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unsigned d = (Fn >> (64 - 8 * x)) & 0x00FF;
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//DEBUG(errs() << "outputing " << hex << d << dec << "\n");
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AtI[2*x] = BUILD_ORi(27, 27, d);
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}
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AtI[17] = BUILD_JMP(31,27,0); //jump, preserving ra, and setting pv
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AtI[18] = 0x00FFFFFF; //mark this as a stub
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}
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void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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//FIXME
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llvm_unreachable(0);
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}
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static TargetJITInfo::JITCompilerFn JITCompilerFunction;
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//static AlphaJITInfo* AlphaJTI;
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extern "C" {
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#ifdef __alpha
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void AlphaCompilationCallbackC(long* oldpv, void* CameFromStub)
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{
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void* Target = JITCompilerFunction(CameFromStub);
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//rewrite the stub to an unconditional branch
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if (((unsigned*)CameFromStub)[18] == 0x00FFFFFF) {
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DEBUG(errs() << "Came from a stub, rewriting\n");
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EmitBranchToAt(CameFromStub, Target);
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} else {
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DEBUG(errs() << "confused, didn't come from stub at " << CameFromStub
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<< " old jump vector " << oldpv
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<< " new jump vector " << Target << "\n");
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}
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//Change pv to new Target
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*oldpv = (long)Target;
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}
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void AlphaCompilationCallback(void);
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asm(
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".text\n"
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".globl AlphaCompilationCallbackC\n"
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".align 4\n"
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".globl AlphaCompilationCallback\n"
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".ent AlphaCompilationCallback\n"
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"AlphaCompilationCallback:\n"
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// //get JIT's GOT
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"ldgp $29, 0($27)\n"
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//Save args, callee saved, and perhaps others?
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//args: $16-$21 $f16-$f21 (12)
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//callee: $9-$14 $f2-$f9 (14)
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//others: fp:$15 ra:$26 pv:$27 (3)
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"lda $30, -232($30)\n"
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"stq $16, 0($30)\n"
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"stq $17, 8($30)\n"
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"stq $18, 16($30)\n"
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"stq $19, 24($30)\n"
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"stq $20, 32($30)\n"
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"stq $21, 40($30)\n"
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"stt $f16, 48($30)\n"
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"stt $f17, 56($30)\n"
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"stt $f18, 64($30)\n"
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"stt $f19, 72($30)\n"
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"stt $f20, 80($30)\n"
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"stt $f21, 88($30)\n"
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"stq $9, 96($30)\n"
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"stq $10, 104($30)\n"
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"stq $11, 112($30)\n"
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"stq $12, 120($30)\n"
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"stq $13, 128($30)\n"
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"stq $14, 136($30)\n"
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"stt $f2, 144($30)\n"
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"stt $f3, 152($30)\n"
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"stt $f4, 160($30)\n"
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"stt $f5, 168($30)\n"
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"stt $f6, 176($30)\n"
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"stt $f7, 184($30)\n"
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"stt $f8, 192($30)\n"
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"stt $f9, 200($30)\n"
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"stq $15, 208($30)\n"
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"stq $26, 216($30)\n"
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"stq $27, 224($30)\n"
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"addq $30, 224, $16\n" //pass the addr of saved pv as the first arg
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"bis $0, $0, $17\n" //pass the roughly stub addr in second arg
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"jsr $26, AlphaCompilationCallbackC\n" //call without saving ra
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"ldq $16, 0($30)\n"
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"ldq $17, 8($30)\n"
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"ldq $18, 16($30)\n"
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"ldq $19, 24($30)\n"
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"ldq $20, 32($30)\n"
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"ldq $21, 40($30)\n"
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"ldt $f16, 48($30)\n"
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"ldt $f17, 56($30)\n"
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"ldt $f18, 64($30)\n"
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"ldt $f19, 72($30)\n"
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"ldt $f20, 80($30)\n"
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"ldt $f21, 88($30)\n"
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"ldq $9, 96($30)\n"
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"ldq $10, 104($30)\n"
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"ldq $11, 112($30)\n"
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"ldq $12, 120($30)\n"
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"ldq $13, 128($30)\n"
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"ldq $14, 136($30)\n"
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"ldt $f2, 144($30)\n"
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"ldt $f3, 152($30)\n"
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"ldt $f4, 160($30)\n"
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"ldt $f5, 168($30)\n"
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"ldt $f6, 176($30)\n"
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"ldt $f7, 184($30)\n"
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"ldt $f8, 192($30)\n"
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"ldt $f9, 200($30)\n"
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"ldq $15, 208($30)\n"
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"ldq $26, 216($30)\n"
|
||||
"ldq $27, 224($30)\n" //this was updated in the callback with the target
|
||||
|
||||
"lda $30, 232($30)\n" //restore sp
|
||||
"jmp $31, ($27)\n" //jump to the new function
|
||||
".end AlphaCompilationCallback\n"
|
||||
);
|
||||
#else
|
||||
void AlphaCompilationCallback() {
|
||||
llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
TargetJITInfo::StubLayout AlphaJITInfo::getStubLayout() {
|
||||
// The stub contains 19 4-byte instructions, aligned at 4 bytes:
|
||||
// R0 = R27
|
||||
// 8 x "R27 <<= 8; R27 |= 8-bits-of-Target" == 16 instructions
|
||||
// JMP R27
|
||||
// Magic number so the compilation callback can recognize the stub.
|
||||
StubLayout Result = {19 * 4, 4};
|
||||
return Result;
|
||||
}
|
||||
|
||||
void *AlphaJITInfo::emitFunctionStub(const Function* F, void *Fn,
|
||||
JITCodeEmitter &JCE) {
|
||||
//assert(Fn == AlphaCompilationCallback && "Where are you going?\n");
|
||||
//Do things in a stupid slow way!
|
||||
void* Addr = (void*)(intptr_t)JCE.getCurrentPCValue();
|
||||
for (int x = 0; x < 19; ++ x)
|
||||
JCE.emitWordLE(0);
|
||||
EmitBranchToAt(Addr, Fn);
|
||||
DEBUG(errs() << "Emitting Stub to " << Fn << " at [" << Addr << "]\n");
|
||||
return Addr;
|
||||
}
|
||||
|
||||
TargetJITInfo::LazyResolverFn
|
||||
AlphaJITInfo::getLazyResolverFunction(JITCompilerFn F) {
|
||||
JITCompilerFunction = F;
|
||||
// setZerothGOTEntry((void*)AlphaCompilationCallback);
|
||||
return AlphaCompilationCallback;
|
||||
}
|
||||
|
||||
//These describe LDAx
|
||||
static const int IMM_LOW = -32768;
|
||||
static const int IMM_HIGH = 32767;
|
||||
static const int IMM_MULT = 65536;
|
||||
|
||||
static long getUpper16(long l)
|
||||
{
|
||||
long y = l / IMM_MULT;
|
||||
if (l % IMM_MULT > IMM_HIGH)
|
||||
++y;
|
||||
if (l % IMM_MULT < IMM_LOW)
|
||||
--y;
|
||||
assert((short)y == y && "displacement out of range");
|
||||
return y;
|
||||
}
|
||||
|
||||
static long getLower16(long l)
|
||||
{
|
||||
long h = getUpper16(l);
|
||||
long y = l - h * IMM_MULT;
|
||||
assert(y == (short)y && "Displacement out of range");
|
||||
return y;
|
||||
}
|
||||
|
||||
void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char* GOTBase) {
|
||||
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
|
||||
unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
|
||||
long idx = 0;
|
||||
bool doCommon = true;
|
||||
switch ((Alpha::RelocationType)MR->getRelocationType()) {
|
||||
default: llvm_unreachable("Unknown relocation type!");
|
||||
case Alpha::reloc_literal:
|
||||
//This is a LDQl
|
||||
idx = MR->getGOTIndex();
|
||||
DEBUG(errs() << "Literal relocation to slot " << idx);
|
||||
idx = (idx - GOToffset) * 8;
|
||||
DEBUG(errs() << " offset " << idx << "\n");
|
||||
break;
|
||||
case Alpha::reloc_gprellow:
|
||||
idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
|
||||
idx = getLower16(idx);
|
||||
DEBUG(errs() << "gprellow relocation offset " << idx << "\n");
|
||||
DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
|
||||
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
|
||||
break;
|
||||
case Alpha::reloc_gprelhigh:
|
||||
idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
|
||||
idx = getUpper16(idx);
|
||||
DEBUG(errs() << "gprelhigh relocation offset " << idx << "\n");
|
||||
DEBUG(errs() << " Pointer is " << (void*)MR->getResultPointer()
|
||||
<< " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
|
||||
break;
|
||||
case Alpha::reloc_gpdist:
|
||||
switch (*RelocPos >> 26) {
|
||||
case 0x09: //LDAH
|
||||
idx = &GOTBase[GOToffset * 8] - (unsigned char*)RelocPos;
|
||||
idx = getUpper16(idx);
|
||||
DEBUG(errs() << "LDAH: " << idx << "\n");
|
||||
//add the relocation to the map
|
||||
gpdistmap[std::make_pair(Function, MR->getConstantVal())] = RelocPos;
|
||||
break;
|
||||
case 0x08: //LDA
|
||||
assert(gpdistmap[std::make_pair(Function, MR->getConstantVal())] &&
|
||||
"LDAg without seeing LDAHg");
|
||||
idx = &GOTBase[GOToffset * 8] -
|
||||
(unsigned char*)gpdistmap[std::make_pair(Function, MR->getConstantVal())];
|
||||
idx = getLower16(idx);
|
||||
DEBUG(errs() << "LDA: " << idx << "\n");
|
||||
break;
|
||||
default:
|
||||
llvm_unreachable("Cannot handle gpdist yet");
|
||||
}
|
||||
break;
|
||||
case Alpha::reloc_bsr: {
|
||||
idx = (((unsigned char*)MR->getResultPointer() -
|
||||
(unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun
|
||||
*RelocPos |= (idx & ((1 << 21)-1));
|
||||
doCommon = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (doCommon) {
|
||||
short x = (short)idx;
|
||||
assert(x == idx);
|
||||
*(short*)RelocPos = x;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,53 +0,0 @@
|
||||
//===- AlphaJITInfo.h - Alpha impl. of the JIT interface ----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the Alpha implementation of the TargetJITInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef ALPHA_JITINFO_H
|
||||
#define ALPHA_JITINFO_H
|
||||
|
||||
#include "llvm/Target/TargetJITInfo.h"
|
||||
#include <map>
|
||||
|
||||
namespace llvm {
|
||||
class TargetMachine;
|
||||
|
||||
class AlphaJITInfo : public TargetJITInfo {
|
||||
protected:
|
||||
TargetMachine &TM;
|
||||
|
||||
//because gpdist are paired and relative to the pc of the first inst,
|
||||
//we need to have some state
|
||||
std::map<std::pair<void*, int>, void*> gpdistmap;
|
||||
public:
|
||||
explicit AlphaJITInfo(TargetMachine &tm) : TM(tm)
|
||||
{ useGOT = true; }
|
||||
|
||||
virtual StubLayout getStubLayout();
|
||||
virtual void *emitFunctionStub(const Function* F, void *Fn,
|
||||
JITCodeEmitter &JCE);
|
||||
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
|
||||
virtual void relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char* GOTBase);
|
||||
|
||||
/// replaceMachineCodeForFunction - Make it so that calling the function
|
||||
/// whose machine code is at OLD turns into a call to NEW, perhaps by
|
||||
/// overwriting OLD with a branch to NEW. This is used for self-modifying
|
||||
/// code.
|
||||
///
|
||||
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
||||
private:
|
||||
static const unsigned GOToffset = 4096;
|
||||
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -11,7 +11,6 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "Alpha.h"
|
||||
#include "AlphaJITInfo.h"
|
||||
#include "AlphaMCAsmInfo.h"
|
||||
#include "AlphaTargetMachine.h"
|
||||
#include "llvm/PassManager.h"
|
||||
@ -30,7 +29,6 @@ AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
|
||||
: LLVMTargetMachine(T, TT),
|
||||
DataLayout("e-f128:128:128-n64"),
|
||||
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
|
||||
JITInfo(*this),
|
||||
Subtarget(TT, FS),
|
||||
TLInfo(*this),
|
||||
TSInfo(*this) {
|
||||
@ -54,9 +52,3 @@ bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
|
||||
PM.add(createAlphaLLRPPass(*this));
|
||||
return false;
|
||||
}
|
||||
bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
|
||||
CodeGenOpt::Level OptLevel,
|
||||
JITCodeEmitter &JCE) {
|
||||
PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -18,7 +18,6 @@
|
||||
#include "llvm/Target/TargetData.h"
|
||||
#include "llvm/Target/TargetFrameInfo.h"
|
||||
#include "AlphaInstrInfo.h"
|
||||
#include "AlphaJITInfo.h"
|
||||
#include "AlphaISelLowering.h"
|
||||
#include "AlphaSelectionDAGInfo.h"
|
||||
#include "AlphaSubtarget.h"
|
||||
@ -31,7 +30,6 @@ class AlphaTargetMachine : public LLVMTargetMachine {
|
||||
const TargetData DataLayout; // Calculates type size & alignment
|
||||
AlphaInstrInfo InstrInfo;
|
||||
TargetFrameInfo FrameInfo;
|
||||
AlphaJITInfo JITInfo;
|
||||
AlphaSubtarget Subtarget;
|
||||
AlphaTargetLowering TLInfo;
|
||||
AlphaSelectionDAGInfo TSInfo;
|
||||
@ -53,15 +51,10 @@ public:
|
||||
return &TSInfo;
|
||||
}
|
||||
virtual const TargetData *getTargetData() const { return &DataLayout; }
|
||||
virtual AlphaJITInfo* getJITInfo() {
|
||||
return &JITInfo;
|
||||
}
|
||||
|
||||
// Pass Pipeline Configuration
|
||||
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
|
||||
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
|
||||
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
|
||||
JITCodeEmitter &JCE);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
@ -91,7 +91,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_Immediate:
|
||||
llvm_unreachable("printOp() does not handle immediate values");
|
||||
assert(0 && "printOp() does not handle immediate values");
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_MachineBasicBlock:
|
||||
|
||||
@ -5,7 +5,6 @@ tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
|
||||
tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(AlphaGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(AlphaGenCallingConv.inc -gen-callingconv)
|
||||
@ -17,7 +16,6 @@ add_llvm_target(AlphaCodeGen
|
||||
AlphaInstrInfo.cpp
|
||||
AlphaISelDAGToDAG.cpp
|
||||
AlphaISelLowering.cpp
|
||||
AlphaJITInfo.cpp
|
||||
AlphaLLRP.cpp
|
||||
AlphaMCAsmInfo.cpp
|
||||
AlphaRegisterInfo.cpp
|
||||
|
||||
@ -14,7 +14,7 @@ TARGET = Alpha
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
|
||||
AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
|
||||
AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \
|
||||
AlphaGenInstrInfo.inc \
|
||||
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
|
||||
AlphaGenCallingConv.inc AlphaGenSubtarget.inc
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user