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Document the shortcomings of DwarfExpression::addMachineReg().

Browse Source 
Also make a drive-by-fix of a bug in the subregister scan code that
only triggers with an incomplete or otherwise very irregular machine
description.

rdar://problem/37404493

llvm-svn: 324972
This commit is contained in:
Adrian Prantl 2018-02-13 01:02:56 +00:00
parent 870f6d17a4
commit 455280bb24
1 changed files with 7 additions and 3 deletions
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10
lib/CodeGen/AsmPrinter/DwarfExpression.cpp
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@ -123,7 +123,10 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
unsigned RegSize = TRI.getRegSizeInBits(*RC);
// Keep track of the bits in the register we already emitted, so we
// can avoid emitting redundant aliasing subregs.
// can avoid emitting redundant aliasing subregs. Because this is
// just doing a greedy scan of all subregisters, it is possible that
// this doesn't find a combination of subregisters that fully cover
// the register (even though one may exist).
SmallBitVector Coverage(RegSize, false);
for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
@ -143,7 +146,7 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
if (CurSubReg.test(Coverage)) {
// Emit a piece for any gap in the coverage.
if (Offset > CurPos)
DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
DwarfRegs.push_back(
{Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
if (Offset >= MaxSize)
@ -154,7 +157,8 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
CurPos = Offset + Size;
}
}
if (CurPos < RegSize)
DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
return CurPos;
}