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Move to thumb2 loads, fixes a problem with incoming registers
as thumb1. Fixes lencod. llvm-svn: 116027
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@ -661,20 +661,19 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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default:
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// This is mostly going to be Neon/vector support.
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return false;
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// Using thumb1 instructions for now, use the appropriate RC.
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case MVT::i16:
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Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
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RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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Opc = isThumb ? ARM::t2LDRHi8 : ARM::LDRH;
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RC = ARM::GPRRegisterClass;
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VT = MVT::i32;
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break;
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case MVT::i8:
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Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
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RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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Opc = isThumb ? ARM::t2LDRBi8 : ARM::LDRB;
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RC = ARM::GPRRegisterClass;
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VT = MVT::i32;
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break;
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case MVT::i32:
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Opc = isThumb ? ARM::tLDR : ARM::LDR;
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RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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Opc = isThumb ? ARM::t2LDRi8 : ARM::LDR;
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::f32:
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Opc = ARM::VLDRS;
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@ -690,18 +689,16 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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ResultReg = createResultReg(RC);
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// TODO: Fix the Addressing modes so that these can share some code.
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// Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
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// The thumb addressing mode has operands swapped from the arm addressing
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// mode, the floating point one only has two operands.
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if (isFloat)
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// For now with the additions above the offset should be zero - thus we
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// can always fit into an i8.
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assert(Offset == 0 && "Offset not zero!");
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// The thumb and floating point instructions both take 2 operands, ARM takes
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// another register.
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Reg).addImm(Offset));
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else if (isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Reg).addImm(Offset).addReg(0));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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