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Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is
possible and the target only supports MULHS. llvm-svn: 30022
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@ -4656,7 +4656,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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break;
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}
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case ISD::MUL: {
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if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
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bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
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bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
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bool UseLibCall = true;
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if (HasMULHS || HasMULHU) {
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SDOperand LL, LH, RL, RH;
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ExpandOp(Node->getOperand(0), LL, LH);
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ExpandOp(Node->getOperand(1), RL, RH);
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@ -4665,7 +4668,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// extended the sign bit of the low half through the upper half, and if so
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// emit a MULHS instead of the alternate sequence that is valid for any
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// i64 x i64 multiply.
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if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
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if (HasMULHS &&
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// is RH an extension of the sign bit of RL?
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RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
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RH.getOperand(1).getOpcode() == ISD::Constant &&
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@ -4675,17 +4678,21 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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LH.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
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Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
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} else {
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UseLibCall = false;
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} else if (HasMULHU) {
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Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
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RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
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LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
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Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
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Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
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UseLibCall = false;
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}
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Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
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} else {
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Lo = ExpandLibCall("__muldi3" , Node, Hi);
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if (!UseLibCall)
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Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
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}
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if (UseLibCall)
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Lo = ExpandLibCall("__muldi3" , Node, Hi);
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break;
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}
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case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
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