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[SelectionDAG] Teach the vector scalarizer about TRUNCATE.
When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> llvm-svn: 190830
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@ -537,7 +537,7 @@ private:
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// Vector Operand Scalarization: <1 x ty> -> ty.
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bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
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SDValue ScalarizeVecOp_BITCAST(SDNode *N);
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SDValue ScalarizeVecOp_EXTEND(SDNode *N);
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SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
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SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
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SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
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@ -371,7 +371,8 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
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case ISD::ANY_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::SIGN_EXTEND:
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Res = ScalarizeVecOp_EXTEND(N);
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case ISD::TRUNCATE:
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Res = ScalarizeVecOp_UnaryOp(N);
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break;
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case ISD::CONCAT_VECTORS:
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Res = ScalarizeVecOp_CONCAT_VECTORS(N);
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@ -410,7 +411,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
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/// ScalarizeVecOp_EXTEND - If the value to extend is a vector that needs
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/// to be scalarized, it must be <1 x ty>. Extend the element instead.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTEND(SDNode *N) {
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SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
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assert(N->getValueType(0).getVectorNumElements() == 1 &&
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"Unexected vector type!");
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SDValue Elt = GetScalarizedVector(N->getOperand(0));
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@ -224,3 +224,23 @@ entry:
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%vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1)
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ret <8 x i16> %vmull.i
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}
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; <rdar://problem/14989896> Make sure we manage to truncate a vector from an
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; illegal type to a legal type.
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define <2 x i8> @test_truncate(<2 x i128> %in) {
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; CHECK-LABEL: test_truncate:
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; CHECK: mov [[BASE:r[0-9]+]], sp
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; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32]
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; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4
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; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32]
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; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we
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; cannot express that.
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; CHECK-NEXT: vmov.32 [[REG2:d[0-9]+]][0], r0
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; CHECK-NEXT: vmov.32 [[REG2]][1], r1
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; The Q register used here should match floor(REG1/2), but we cannot express that.
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; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}}
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; CHECK-NEXT: vmov r0, r1, [[RES]]
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entry:
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%res = trunc <2 x i128> %in to <2 x i8>
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ret <2 x i8> %res
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}
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