RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-28 06:27:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

As requested, a blurb on sub-targets.

Browse Source 
llvm-svn: 23769
This commit is contained in:
Jim Laskey 2005-10-17 12:19:10 +00:00
parent 31d368acdc
commit 47bcddb491
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
docs/CodeGenerator.html
View File

@ -444,7 +444,11 @@ href="TableGenFundamentals.html">TableGen</a> description of the register file.
<div class="doc_text">
<p>
TODO
<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
specific chip set being targeted. A sub-target informs code generation of
which instructions are supported, instruction latencies and instruction
execution itinerary; i.e., which processing units are used, in what order, and
for how long.
</p>
</div>