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[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs

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Differential Revision: http://reviews.llvm.org/D20081

llvm-svn: 270594
This commit is contained in:
Konstantin Zhuravlyov 2016-05-24 18:37:18 +00:00
parent ad9a9a6f5e
commit 480521dd43
8 changed files with 26 additions and 26 deletions
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8
lib/Target/AMDGPU/AMDGPU.td
View File

@ -328,11 +328,11 @@ def FeatureDebuggerInsertNops : SubtargetFeature<
"Insert one nop instruction for each high level source statement"
>;
def FeatureDebuggerReserveTrapRegs : SubtargetFeature<
"amdgpu-debugger-reserve-trap-regs",
"DebuggerReserveTrapVGPRs",
def FeatureDebuggerReserveRegs : SubtargetFeature<
"amdgpu-debugger-reserve-regs",
"DebuggerReserveRegs",
"true",
"Reserve VGPRs for trap handler usage"
"Reserve registers for debugger usage"
>;
//===----------------------------------------------------------------------===//

11
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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@ -435,12 +435,13 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
MaxSGPR += ExtraSGPRs;
// Update necessary Reserved* fields and max VGPRs used if
// "amdgpu-debugger-reserve-trap-regs" attribute was specified.
if (STM.debuggerReserveTrapVGPRs()) {
// Record first reserved register and reserved register count fields, and
// update max register counts if "amdgpu-debugger-reserve-regs" attribute was
// specified.
if (STM.debuggerReserveRegs()) {
ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
ProgInfo.ReservedVGPRCount = MFI->getDebuggerReservedVGPRCount();
MaxVGPR += MFI->getDebuggerReservedVGPRCount();
}
// We found the maximum register index. They start at 0, so add one to get the

2
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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@ -98,7 +98,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
LDSBankCount(0),
IsaVersion(ISAVersion0_0_0),
EnableSIScheduler(false),
DebuggerInsertNops(false), DebuggerReserveTrapVGPRs(false),
DebuggerInsertNops(false), DebuggerReserveRegs(false),
FrameLowering(nullptr),
GISel(),
InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {

6
lib/Target/AMDGPU/AMDGPUSubtarget.h
View File

@ -96,7 +96,7 @@ private:
unsigned IsaVersion;
bool EnableSIScheduler;
bool DebuggerInsertNops;
bool DebuggerReserveTrapVGPRs;
bool DebuggerReserveRegs;
std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
std::unique_ptr<AMDGPUTargetLowering> TLInfo;
@ -319,8 +319,8 @@ public:
return DebuggerInsertNops;
}
bool debuggerReserveTrapVGPRs() const {
return DebuggerReserveTrapVGPRs;
bool debuggerReserveRegs() const {
return DebuggerReserveRegs;
}
bool dumpCode() const {

6
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
View File

@ -49,7 +49,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
PSInputAddr(0),
ReturnsVoid(true),
MaximumWorkGroupSize(0),
DebuggerReserveTrapVGPRCount(0),
DebuggerReservedVGPRCount(0),
LDSWaveSpillSize(0),
PSInputEna(0),
NumUserSGPRs(0),
@ -134,8 +134,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
else
MaximumWorkGroupSize = ST.getWavefrontSize();
if (ST.debuggerReserveTrapVGPRs())
DebuggerReserveTrapVGPRCount = 4;
if (ST.debuggerReserveRegs())
DebuggerReservedVGPRCount = 4;
}
unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(

9
lib/Target/AMDGPU/SIMachineFunctionInfo.h
View File

@ -62,8 +62,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
unsigned MaximumWorkGroupSize;
// Number of reserved VGPRs for trap handler usage.
unsigned DebuggerReserveTrapVGPRCount;
// Number of reserved VGPRs for debugger usage.
unsigned DebuggerReservedVGPRCount;
public:
// FIXME: Make private
@ -329,8 +329,9 @@ public:
ReturnsVoid = Value;
}
unsigned getDebuggerReserveTrapVGPRCount() const {
return DebuggerReserveTrapVGPRCount;
/// \returns Number of reserved VGPRs for debugger usage.
unsigned getDebuggerReservedVGPRCount() const {
return DebuggerReservedVGPRCount;
}
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;

6
lib/Target/AMDGPU/SIRegisterInfo.cpp
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@ -193,12 +193,12 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
assert(!isSubRegister(ScratchRSrcReg, ScratchWaveOffsetReg));
}
// Reserve VGPRs for trap handler usage if "amdgpu-debugger-reserve-trap-regs"
// Reserve registers for debugger usage if "amdgpu-debugger-reserve-trap-regs"
// attribute was specified.
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
if (ST.debuggerReserveTrapVGPRs()) {
if (ST.debuggerReserveRegs()) {
unsigned ReservedVGPRFirst =
MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
MaxWorkGroupVGPRCount - MFI->getDebuggerReservedVGPRCount();
for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);

4
test/CodeGen/AMDGPU/debugger-reserve-regs.ll
View File

@ -1,8 +1,6 @@
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-trap-regs -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s
; CHECK: reserved_vgpr_first = {{[0-9]+}}
; CHECK-NEXT: reserved_vgpr_count = 4
; CHECK: ReservedVGPRFirst: {{[0-9]+}}
; CHECK-NEXT: ReservedVGPRCount: 4