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AMDGPU: Add some tests for inlineasm behavior

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llvm-svn: 361332
This commit is contained in:
Matt Arsenault 2019-05-21 23:23:12 +00:00
parent 7442d406a0
commit 48243e2e94
1 changed files with 43 additions and 0 deletions
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43
test/CodeGen/AMDGPU/endpgm-dce.mir
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@ -313,3 +313,46 @@ body: |
S_ENDPGM 0, implicit %3
...
---
# GCN-LABEL: name: inlineasm_nosideeffect
# GCN-NOT: S_OR_B64
# GCN-NOT: INLINEASM
# GCN: S_ENDPGM 0
name: inlineasm_nosideeffect
tracksRegLiveness: true
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
body: |
bb.0:
$vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%2:sreg_64 = IMPLICIT_DEF
INLINEASM &"", 0, 0
S_ENDPGM 0
...
---
# GCN-LABEL: name: inlineasm_sideeffect
# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN-NEXT: IMPLICIT_DEF
# GCN-NEXT: INLINEASM
# GCN-NEXT: S_ENDPGM 0
name: inlineasm_sideeffect
tracksRegLiveness: true
registers:
- { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 }
body: |
bb.0:
$vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%2:sreg_64 = IMPLICIT_DEF
INLINEASM &"", 1, 0
S_ENDPGM 0
...