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[TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take an MVT instead of an EVT. NFC

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The main caller of this already has an MVT and several targets called getSimpleVT inside without checking isSimple. This makes the simpleness explicit.

llvm-svn: 346180
This commit is contained in:
Craig Topper 2018-11-05 23:26:13 +00:00
parent 085d608821
commit 487ffb554f
14 changed files with 18 additions and 19 deletions
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2
include/llvm/CodeGen/TargetLowering.h
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@ -279,7 +279,7 @@ public:
/// Return the preferred vector type legalization action.
virtual TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const {
getPreferredVectorAction(MVT VT) const {
// The default action for one element vectors is to scalarize
if (VT.getVectorNumElements() == 1)
return TypeScalarizeVector;

7
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -11506,12 +11506,11 @@ unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
}
TargetLoweringBase::LegalizeTypeAction
AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
MVT SVT = VT.getSimpleVT();
AArch64TargetLowering::getPreferredVectorAction(MVT VT) const {
// During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
// v4i16, v2i32 instead of to promote.
if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
|| SVT == MVT::v1f32)
if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 ||
VT == MVT::v1f32)
return TypeWidenVector;
return TargetLoweringBase::getPreferredVectorAction(VT);

2
lib/Target/AArch64/AArch64ISelLowering.h
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@ -395,7 +395,7 @@ public:
bool useLoadStackGuardNode() const override;
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const override;
getPreferredVectorAction(MVT VT) const override;
/// If the target has a standard location for the stack protector cookie,
/// returns the address of that location. Otherwise, returns nullptr.

2
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -1185,7 +1185,7 @@ bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
}
TargetLoweringBase::LegalizeTypeAction
SITargetLowering::getPreferredVectorAction(EVT VT) const {
SITargetLowering::getPreferredVectorAction(MVT VT) const {
if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
return TypeSplitVector;

2
lib/Target/AMDGPU/SIISelLowering.h
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@ -234,7 +234,7 @@ public:
bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const override;
getPreferredVectorAction(MVT VT) const override;
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;

4
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1834,12 +1834,12 @@ bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
}
TargetLoweringBase::LegalizeTypeAction
HexagonTargetLowering::getPreferredVectorAction(EVT VT) const {
HexagonTargetLowering::getPreferredVectorAction(MVT VT) const {
if (VT.getVectorNumElements() == 1)
return TargetLoweringBase::TypeScalarizeVector;
// Always widen vectors of i1.
MVT ElemTy = VT.getSimpleVT().getVectorElementType();
MVT ElemTy = VT.getVectorElementType();
if (ElemTy == MVT::i1)
return TargetLoweringBase::TypeWidenVector;

2
lib/Target/Hexagon/HexagonISelLowering.h
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@ -141,7 +141,7 @@ namespace HexagonISD {
unsigned DefinedValues) const override;
bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

2
lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
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@ -54,7 +54,7 @@ bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const {
return false;
if (ST.isHVXVectorType(VecVT.getSimpleVT()))
return true;
auto Action = TLI.getPreferredVectorAction(VecVT);
auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
return Action == TargetLoweringBase::TypeWidenVector;
}

2
lib/Target/NVPTX/NVPTXISelLowering.cpp
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@ -1170,7 +1170,7 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
TargetLoweringBase::LegalizeTypeAction
NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const {
if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
return TypeSplitVector;
if (VT == MVT::v2f16)

2
lib/Target/NVPTX/NVPTXISelLowering.h
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@ -511,7 +511,7 @@ public:
}
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const override;
getPreferredVectorAction(MVT VT) const override;
// Get the degree of precision we want from 32-bit floating point division
// operations.

2
lib/Target/PowerPC/PPCISelLowering.h
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@ -569,7 +569,7 @@ namespace llvm {
/// of v4i8's and shuffle them. This will turn into a mess of 8 extending
/// loads, moves back into VSR's (or memory ops if we don't have moves) and
/// then the VPERM for the shuffle. All in all a very slow sequence.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
const override {
if (VT.getScalarSizeInBits() % 8 == 0)
return TypeWidenVector;

2
lib/Target/SystemZ/SystemZISelLowering.h
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@ -379,7 +379,7 @@ public:
// want to clobber the upper 32 bits of a GPR unnecessarily.
return MVT::i32;
}
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
const override {
// Widen subvectors to the full width rather than promoting integer
// elements. This is better because:

4
lib/Target/X86/X86ISelLowering.cpp
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@ -1787,13 +1787,13 @@ SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
}
TargetLoweringBase::LegalizeTypeAction
X86TargetLowering::getPreferredVectorAction(EVT VT) const {
X86TargetLowering::getPreferredVectorAction(MVT VT) const {
if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
return TypeSplitVector;
if (ExperimentalVectorWideningLegalization &&
VT.getVectorNumElements() != 1 &&
VT.getVectorElementType().getSimpleVT() != MVT::i1)
VT.getVectorElementType() != MVT::i1)
return TypeWidenVector;
return TargetLoweringBase::getPreferredVectorAction(VT);

2
lib/Target/X86/X86ISelLowering.h
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@ -1113,7 +1113,7 @@ namespace llvm {
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
/// Customize the preferred legalization strategy for certain types.
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
EVT VT) const override;