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[DSE,MemorySSA] Handle atomicrmw/cmpxchg conservatively.
This adds conservative handling of AtomicRMW/AtomicCmpXChg to isDSEBarrier, similar to atomic loads and stores.
This commit is contained in:
Florian Hahn
parent
2893862e92
commit
48a439a77a
@ -2061,6 +2061,11 @@ struct DSEState {
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return isStrongerThanMonotonic(LI->getOrdering());
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return isStrongerThanMonotonic(LI->getOrdering());
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if (auto *SI = dyn_cast<StoreInst>(NI))
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if (auto *SI = dyn_cast<StoreInst>(NI))
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return isStrongerThanMonotonic(SI->getOrdering());
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return isStrongerThanMonotonic(SI->getOrdering());
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if (auto *ARMW = dyn_cast<AtomicRMWInst>(NI))
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return isStrongerThanMonotonic(ARMW->getOrdering());
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if (auto *CmpXchg = dyn_cast<AtomicCmpXchgInst>(NI))
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return isStrongerThanMonotonic(CmpXchg->getSuccessOrdering()) ||
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isStrongerThanMonotonic(CmpXchg->getFailureOrdering());
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llvm_unreachable("other instructions should be skipped in MemorySSA");
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llvm_unreachable("other instructions should be skipped in MemorySSA");
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}
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}
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return false;
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return false;
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@ -132,6 +132,157 @@ define i32 @test15() {
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ret i32 %x
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ret i32 %x
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}
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}
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@z = common global i64 0, align 4
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@a = common global i64 0, align 4
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; Be conservative, do not kill regular store.
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define i64 @test_atomicrmw_0() {
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; CHECK-LABEL: @test_atomicrmw_0(
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; CHECK-NEXT: store i64 1, i64* @z, align 8
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* @z, i64 -1 monotonic
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* @z, i64 -1 monotonic
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ret i64 %res
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}
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; Be conservative, do not kill regular store.
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define i64 @test_atomicrmw_1() {
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; CHECK-LABEL: @test_atomicrmw_1(
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; CHECK-NEXT: store i64 1, i64* @z, align 8
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* @z, i64 -1 acq_rel
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* @z, i64 -1 acq_rel
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ret i64 %res
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}
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; Monotonic atomicrmw should not block eliminating no-aliasing stores.
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define i64 @test_atomicrmw_2() {
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; CHECK-LABEL: @test_atomicrmw_2(
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* @a, i64 -1 monotonic
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; CHECK-NEXT: store i64 2, i64* @z, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* @a, i64 -1 monotonic
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store i64 2, i64* @z
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ret i64 %res
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}
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; Be conservative, do not eliminate stores across atomic operations > monotonic.
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define i64 @test_atomicrmw_3() {
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; CHECK-LABEL: @test_atomicrmw_3(
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; CHECK-NEXT: store i64 1, i64* @z, align 8
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* @a, i64 -1 release
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; CHECK-NEXT: store i64 2, i64* @z, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* @a, i64 -1 release
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store i64 2, i64* @z
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ret i64 %res
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}
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; Be conservative, do not eliminate may-alias stores.
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define i64 @test_atomicrmw_4(i64* %ptr) {
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; CHECK-LABEL: @test_atomicrmw_4(
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; CHECK-NEXT: store i64 1, i64* @z, align 8
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* [[PTR:%.*]], i64 -1 monotonic
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; CHECK-NEXT: store i64 2, i64* @z, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* %ptr, i64 -1 monotonic
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store i64 2, i64* @z
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ret i64 %res
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}
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; Be conservative, do not eliminate aliasing stores.
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define i64 @test_atomicrmw_5() {
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; CHECK-LABEL: @test_atomicrmw_5(
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; CHECK-NEXT: store i64 1, i64* @z, align 8
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; CHECK-NEXT: [[RES:%.*]] = atomicrmw add i64* @z, i64 -1 monotonic
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; CHECK-NEXT: store i64 2, i64* @z, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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store i64 1, i64* @z
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%res = atomicrmw add i64* @z, i64 -1 monotonic
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store i64 2, i64* @z
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ret i64 %res
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}
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; Be conservative, do not eliminate non-monotonic cmpxchg.
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define { i32, i1} @test_cmpxchg_1() {
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; CHECK-LABEL: @test_cmpxchg_1(
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; CHECK-NEXT: store i32 1, i32* @x, align 4
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; CHECK-NEXT: [[RET:%.*]] = cmpxchg volatile i32* @x, i32 10, i32 20 seq_cst monotonic
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; CHECK-NEXT: store i32 2, i32* @x, align 4
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; CHECK-NEXT: ret { i32, i1 } [[RET]]
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;
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store i32 1, i32* @x
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%ret = cmpxchg volatile i32* @x, i32 10, i32 20 seq_cst monotonic
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store i32 2, i32* @x
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ret { i32, i1 } %ret
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}
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; Monotonic cmpxchg should not block DSE for non-aliasing stores.
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define { i32, i1} @test_cmpxchg_2() {
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; CHECK-LABEL: @test_cmpxchg_2(
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; CHECK-NEXT: [[RET:%.*]] = cmpxchg volatile i32* @y, i32 10, i32 20 monotonic monotonic
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; CHECK-NEXT: store i32 2, i32* @x, align 4
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; CHECK-NEXT: ret { i32, i1 } [[RET]]
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;
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store i32 1, i32* @x
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%ret = cmpxchg volatile i32* @y, i32 10, i32 20 monotonic monotonic
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store i32 2, i32* @x
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ret { i32, i1 } %ret
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}
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; Be conservative, do not eliminate non-monotonic cmpxchg.
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define { i32, i1} @test_cmpxchg_3() {
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; CHECK-LABEL: @test_cmpxchg_3(
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; CHECK-NEXT: store i32 1, i32* @x, align 4
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; CHECK-NEXT: [[RET:%.*]] = cmpxchg volatile i32* @y, i32 10, i32 20 seq_cst seq_cst
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; CHECK-NEXT: store i32 2, i32* @x, align 4
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; CHECK-NEXT: ret { i32, i1 } [[RET]]
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;
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store i32 1, i32* @x
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%ret = cmpxchg volatile i32* @y, i32 10, i32 20 seq_cst seq_cst
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store i32 2, i32* @x
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ret { i32, i1 } %ret
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}
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; Be conservative, do not eliminate may-alias stores.
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define { i32, i1} @test_cmpxchg_4(i32* %ptr) {
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; CHECK-LABEL: @test_cmpxchg_4(
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; CHECK-NEXT: store i32 1, i32* @x, align 4
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; CHECK-NEXT: [[RET:%.*]] = cmpxchg volatile i32* [[PTR:%.*]], i32 10, i32 20 monotonic monotonic
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; CHECK-NEXT: store i32 2, i32* @x, align 4
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; CHECK-NEXT: ret { i32, i1 } [[RET]]
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;
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store i32 1, i32* @x
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%ret = cmpxchg volatile i32* %ptr, i32 10, i32 20 monotonic monotonic
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store i32 2, i32* @x
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ret { i32, i1 } %ret
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}
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; Be conservative, do not eliminate alias stores.
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define { i32, i1} @test_cmpxchg_5(i32* %ptr) {
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; CHECK-LABEL: @test_cmpxchg_5(
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; CHECK-NEXT: store i32 1, i32* @x, align 4
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; CHECK-NEXT: [[RET:%.*]] = cmpxchg volatile i32* @x, i32 10, i32 20 monotonic monotonic
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; CHECK-NEXT: store i32 2, i32* @x, align 4
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; CHECK-NEXT: ret { i32, i1 } [[RET]]
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;
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store i32 1, i32* @x
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%ret = cmpxchg volatile i32* @x, i32 10, i32 20 monotonic monotonic
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store i32 2, i32* @x
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ret { i32, i1 } %ret
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}
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; **** Noop load->store tests **************************************************
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; **** Noop load->store tests **************************************************
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; We can optimize unordered atomic loads or stores.
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; We can optimize unordered atomic loads or stores.
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