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[RISCV] Recognise riscv32 and riscv64 in triple parsing code

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This is the first in a series of 10 initial patches that incrementally add an 
MC layer for RISC-V to LLVM. See 
<http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> for more 
discussion.

Differential Revision: https://reviews.llvm.org/D23557

llvm-svn: 285707
This commit is contained in:
Alex Bradbury 2016-11-01 16:47:54 +00:00
parent 409807182b
commit 4a18531531
3 changed files with 59 additions and 0 deletions
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2
include/llvm/ADT/Triple.h
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@ -64,6 +64,8 @@ public:
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs
riscv32, // RISC-V (32-bit): riscv32
riscv64, // RISC-V (64-bit): riscv64
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant

21
lib/Support/Triple.cpp
View File

@ -39,6 +39,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case ppc: return "powerpc";
case r600: return "r600";
case amdgcn: return "amdgcn";
case riscv32: return "riscv32";
case riscv64: return "riscv64";
case sparc: return "sparc";
case sparcv9: return "sparcv9";
case sparcel: return "sparcel";
@ -134,6 +136,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case shave: return "shave";
case wasm32:
case wasm64: return "wasm";
case riscv32:
case riscv64: return "riscv";
}
}
@ -261,6 +266,8 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("ppc64le", ppc64le)
.Case("r600", r600)
.Case("amdgcn", amdgcn)
.Case("riscv32", riscv32)
.Case("riscv64", riscv64)
.Case("hexagon", hexagon)
.Case("sparc", sparc)
.Case("sparcel", sparcel)
@ -376,6 +383,8 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("mips64el", Triple::mips64el)
.Case("r600", Triple::r600)
.Case("amdgcn", Triple::amdgcn)
.Case("riscv32", Triple::riscv32)
.Case("riscv64", Triple::riscv64)
.Case("hexagon", Triple::hexagon)
.Cases("s390x", "systemz", Triple::systemz)
.Case("sparc", Triple::sparc)
@ -613,6 +622,8 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::r600:
case Triple::renderscript32:
case Triple::renderscript64:
case Triple::riscv32:
case Triple::riscv64:
case Triple::shave:
case Triple::sparc:
case Triple::sparcel:
@ -1140,6 +1151,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx:
case llvm::Triple::ppc:
case llvm::Triple::r600:
case llvm::Triple::riscv32:
case llvm::Triple::sparc:
case llvm::Triple::sparcel:
case llvm::Triple::tce:
@ -1168,6 +1180,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx64:
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
case llvm::Triple::riscv64:
case llvm::Triple::sparcv9:
case llvm::Triple::systemz:
case llvm::Triple::x86_64:
@ -1220,6 +1233,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx:
case Triple::ppc:
case Triple::r600:
case Triple::riscv32:
case Triple::sparc:
case Triple::sparcel:
case Triple::tce:
@ -1242,6 +1256,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx64: T.setArch(Triple::nvptx); break;
case Triple::ppc64: T.setArch(Triple::ppc); break;
case Triple::sparcv9: T.setArch(Triple::sparc); break;
case Triple::riscv64: T.setArch(Triple::riscv32); break;
case Triple::x86_64: T.setArch(Triple::x86); break;
case Triple::amdil64: T.setArch(Triple::amdil); break;
case Triple::hsail64: T.setArch(Triple::hsail); break;
@ -1283,6 +1298,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx64:
case Triple::ppc64:
case Triple::ppc64le:
case Triple::riscv64:
case Triple::sparcv9:
case Triple::systemz:
case Triple::x86_64:
@ -1299,6 +1315,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx: T.setArch(Triple::nvptx64); break;
case Triple::ppc: T.setArch(Triple::ppc64); break;
case Triple::sparc: T.setArch(Triple::sparcv9); break;
case Triple::riscv32: T.setArch(Triple::riscv64); break;
case Triple::x86: T.setArch(Triple::x86_64); break;
case Triple::amdil: T.setArch(Triple::amdil64); break;
case Triple::hsail: T.setArch(Triple::hsail64); break;
@ -1332,6 +1349,8 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::nvptx64:
case Triple::nvptx:
case Triple::r600:
case Triple::riscv32:
case Triple::riscv64:
case Triple::shave:
case Triple::spir64:
case Triple::spir:
@ -1416,6 +1435,8 @@ bool Triple::isLittleEndian() const {
case Triple::nvptx:
case Triple::ppc64le:
case Triple::r600:
case Triple::riscv32:
case Triple::riscv64:
case Triple::shave:
case Triple::sparcel:
case Triple::spir64:

36
unittests/ADT/TripleTest.cpp
View File

@ -266,6 +266,24 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::AMDHSA, T.getOS());
EXPECT_EQ(Triple::OpenCL, T.getEnvironment());
T = Triple("riscv32-unknown-unknown");
EXPECT_EQ(Triple::riscv32, T.getArch());
EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
EXPECT_EQ(Triple::UnknownOS, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("riscv64-unknown-linux");
EXPECT_EQ(Triple::riscv64, T.getArch());
EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
EXPECT_EQ(Triple::Linux, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("riscv64-unknown-freebsd");
EXPECT_EQ(Triple::riscv64, T.getArch());
EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
EXPECT_EQ(Triple::FreeBSD, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
T = Triple("huh");
EXPECT_EQ(Triple::UnknownArch, T.getArch());
}
@ -559,6 +577,16 @@ TEST(TripleTest, BitWidthPredicates) {
EXPECT_FALSE(T.isArch16Bit());
EXPECT_TRUE(T.isArch32Bit());
EXPECT_FALSE(T.isArch64Bit());
T.setArch(Triple::riscv32);
EXPECT_FALSE(T.isArch16Bit());
EXPECT_TRUE(T.isArch32Bit());
EXPECT_FALSE(T.isArch64Bit());
T.setArch(Triple::riscv64);
EXPECT_FALSE(T.isArch16Bit());
EXPECT_FALSE(T.isArch32Bit());
EXPECT_TRUE(T.isArch64Bit());
}
TEST(TripleTest, BitWidthArchVariants) {
@ -649,6 +677,14 @@ TEST(TripleTest, BitWidthArchVariants) {
T.setArch(Triple::wasm64);
EXPECT_EQ(Triple::wasm32, T.get32BitArchVariant().getArch());
EXPECT_EQ(Triple::wasm64, T.get64BitArchVariant().getArch());
T.setArch(Triple::riscv32);
EXPECT_EQ(Triple::riscv32, T.get32BitArchVariant().getArch());
EXPECT_EQ(Triple::riscv64, T.get64BitArchVariant().getArch());
T.setArch(Triple::riscv64);
EXPECT_EQ(Triple::riscv32, T.get32BitArchVariant().getArch());
EXPECT_EQ(Triple::riscv64, T.get64BitArchVariant().getArch());
}
TEST(TripleTest, EndianArchVariants) {