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ExecutionDepsFix refactoring:
- clang-format This is the one of multiple patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869 Most of the patches are intended at refactoring the existent code. Additional relevant reviews: https://reviews.llvm.org/D40330 https://reviews.llvm.org/D40332 https://reviews.llvm.org/D40333 https://reviews.llvm.org/D40334 Differential Revision: https://reviews.llvm.org/D40331 Change-Id: I131b126af13bc743bc5d69d83699e52b9b720979 llvm-svn: 323093
This commit is contained in:
Marina Yatsina
parent
601fd0ed78
commit
4a883f1d3e
@ -66,7 +66,7 @@ struct DomainValue {
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DomainValue *Next;
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/// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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SmallVector<MachineInstr *, 8> Instrs;
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DomainValue() { clear(); }
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@ -83,14 +83,10 @@ struct DomainValue {
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}
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/// Mark domain as available.
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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}
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void addDomain(unsigned domain) { AvailableDomains |= 1u << domain; }
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// Restrict to a single domain available.
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void setSingleDomain(unsigned domain) {
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AvailableDomains = 1u << domain;
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}
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void setSingleDomain(unsigned domain) { AvailableDomains = 1u << domain; }
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/// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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@ -112,20 +108,20 @@ struct DomainValue {
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/// This class provides the basic blocks traversal order used by passes like
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/// ReachingDefAnalysis and ExecutionDomainFix.
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/// It identifies basic blocks that are part of loops and should to be visited twice
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/// and returns efficient traversal order for all the blocks.
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/// It identifies basic blocks that are part of loops and should to be visited
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/// twice and returns efficient traversal order for all the blocks.
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///
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/// We want to visit every instruction in every basic block in order to update
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/// it's execution domain or collect clearance information. However, for the
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/// clearance calculation, we need to know clearances from all predecessors
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/// (including any backedges), therfore we need to visit some blocks twice.
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/// (including any backedges), therfore we need to visit some blocks twice.
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/// As an example, consider the following loop.
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///
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///
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///
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///
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/// PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
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/// ^ |
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/// +----------------------------------+
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///
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///
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/// The iteration order this pass will return is as follows:
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/// Optimized: PH A B C A' B' C' D
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///
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@ -172,10 +168,10 @@ public:
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struct TraversedMBBInfo {
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/// The basic block.
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MachineBasicBlock *MBB = nullptr;
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/// True if this is the first time we process the basic block.
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bool PrimaryPass = true;
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/// True if the block that is ready for its final round of processing.
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bool IsDone = true;
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@ -185,7 +181,7 @@ public:
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};
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LoopTraversal() {}
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/// \brief Identifies basic blocks that are part of loops and should to be
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/// \brief Identifies basic blocks that are part of loops and should to be
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/// visited twise and returns efficient traversal order for all the blocks.
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typedef SmallVector<TraversedMBBInfo, 4> TraversalOrder;
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TraversalOrder traverse(MachineFunction &MF);
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@ -193,7 +189,6 @@ public:
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private:
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/// Returens true if the block is ready for its final round of processing.
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bool isBlockDone(MachineBasicBlock *MBB);
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};
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/// This class provides the reaching def analysis.
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@ -204,9 +199,9 @@ private:
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const TargetRegisterInfo *TRI;
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unsigned NumRegUnits;
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/// Instruction that defined each register, relative to the beginning of the
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/// current basic block. When a LiveRegsDefInfo is used to represent a live-out
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/// register, this value is relative to the end of the basic block, so it
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/// will be a negative number.
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/// current basic block. When a LiveRegsDefInfo is used to represent a
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/// live-out register, this value is relative to the end of the basic block,
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/// so it will be a negative number.
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using LiveRegsDefInfo = std::vector<int>;
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LiveRegsDefInfo LiveRegs;
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@ -258,7 +253,7 @@ public:
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/// Provides the instruction id of the closest reaching def instruction of
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/// PhysReg that reaches MI, relative to the begining of MI's basic block.
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int getReachingDef(MachineInstr *MI, int PhysReg);
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/// Provides the clearance - the number of instructions since the closest
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/// reaching def instuction of PhysReg that reaches MI.
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int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
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@ -280,7 +275,7 @@ private:
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class ExecutionDomainFix : public MachineFunctionPass {
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SpecificBumpPtrAllocator<DomainValue> Allocator;
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SmallVector<DomainValue*,16> Avail;
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SmallVector<DomainValue *, 16> Avail;
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const TargetRegisterClass *const RC;
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MachineFunction *MF;
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@ -302,7 +297,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
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public:
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ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
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: MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
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: MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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@ -328,21 +323,22 @@ private:
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/// Add reference to DV.
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DomainValue *retain(DomainValue *DV) {
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if (DV) ++DV->Refs;
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if (DV)
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++DV->Refs;
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return DV;
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}
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/// Release a reference to DV. When the last reference is released,
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/// collapse if needed.
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void release(DomainValue*);
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void release(DomainValue *);
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/// Follow the chain of dead DomainValues until a live DomainValue is reached.
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/// Update the referenced pointer when necessary.
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DomainValue *resolve(DomainValue*&);
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DomainValue *resolve(DomainValue *&);
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void setLiveReg(int rx, DomainValue *DV);
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/// Kill register rx, recycle or collapse any DomainValue.
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void kill(int rx);
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@ -352,19 +348,19 @@ private:
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void collapse(DomainValue *dv, unsigned domain);
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/// All instructions and registers in B are moved to A, and B is released.
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bool merge(DomainValue *A, DomainValue *B);
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/// Set up LiveRegs by merging predecessor live-out values.
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void enterBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update live-out values.
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void leaveBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Process he given basic block.
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void processBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Visit given insturcion.
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bool visitInstr(MachineInstr *);
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@ -373,11 +369,11 @@ private:
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void processDefs(MachineInstr *, bool Kill);
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/// A soft instruction can be changed to work in other domains given by mask.
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitSoftInstr(MachineInstr *, unsigned mask);
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/// A hard instruction only works in one domain. All input registers will be
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/// forced into that domain.
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void visitHardInstr(MachineInstr*, unsigned domain);
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void visitHardInstr(MachineInstr *, unsigned domain);
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};
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class BreakFalseDeps : public MachineFunctionPass {
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@ -431,18 +427,18 @@ private:
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bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref);
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/// \brief Return true to if it makes sense to break dependence on a partial def
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/// or undef use.
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bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
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/// \brief Return true to if it makes sense to break dependence on a partial
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/// def or undef use.
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bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
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/// \brief Break false dependencies on undefined register reads.
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/// Walk the block backward computing precise liveness. This is expensive, so we
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/// only do it on demand. Note that the occurrence of undefined register reads
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/// that should be broken is very rare, but when they occur we may have many in
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/// a single block.
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void processUndefReads(MachineBasicBlock*);
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/// Walk the block backward computing precise liveness. This is expensive, so
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/// we only do it on demand. Note that the occurrence of undefined register
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/// reads that should be broken is very rare, but when they occur we may have
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/// many in a single block.
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void processUndefReads(MachineBasicBlock *);
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};
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} // end namepsace llvm
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} // namespace llvm
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#endif // LLVM_CODEGEN_EXECUTIONDEPSFIX_H
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@ -35,9 +35,8 @@ ExecutionDomainFix::regIndices(unsigned Reg) const {
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}
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DomainValue *ExecutionDomainFix::alloc(int domain) {
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DomainValue *dv = Avail.empty() ?
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new(Allocator.Allocate()) DomainValue :
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Avail.pop_back_val();
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DomainValue *dv = Avail.empty() ? new (Allocator.Allocate()) DomainValue
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: Avail.pop_back_val();
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if (domain >= 0)
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dv->addDomain(domain);
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assert(dv->Refs == 0 && "Reference count wasn't cleared");
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@ -69,7 +68,8 @@ DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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return DV;
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// DV has a chain. Find the end.
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do DV = DV->Next;
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do
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DV = DV->Next;
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while (DV->Next);
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// Update DVRef to point to DV.
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@ -166,7 +166,8 @@ void ReachingDefAnalysis::enterBasicBlock(
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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int MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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MBBReachingDefs[MBBNumber].resize(NumRegUnits);
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// Reset instruction counter in each basic block.
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@ -193,10 +194,10 @@ void ReachingDefAnalysis::enterBasicBlock(
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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const LiveRegsDefInfo& Incoming = MBBOutRegsInfos[pred->getNumber()];
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const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming.empty())
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@ -205,14 +206,14 @@ void ReachingDefAnalysis::enterBasicBlock(
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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// Use the most recent predecessor def for each register.
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LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]);
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if ((LiveRegs[Unit] != ReachingDedDefaultVal))
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if ((LiveRegs[Unit] != ReachingDedDefaultVal))
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MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit]);
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}
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}
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DEBUG(
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dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n" : ": all preds known\n"));
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DEBUG(dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n"
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: ": all preds known\n"));
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}
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void ExecutionDomainFix::enterBasicBlock(
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@ -232,10 +233,10 @@ void ExecutionDomainFix::enterBasicBlock(
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock* pred : MBB->predecessors()) {
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(pred->getNumber() < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveRegsDVInfo& Incoming = MBBOutRegsInfos[pred->getNumber()];
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveRegsDVInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming.empty())
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@ -266,16 +267,17 @@ void ExecutionDomainFix::enterBasicBlock(
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force(rx, pdv->getFirstDomain());
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}
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}
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DEBUG(
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dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n" : ": all preds known\n"));
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DEBUG(dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n"
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: ": all preds known\n"));
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}
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void ReachingDefAnalysis::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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assert(MBBNumber < MBBOutRegsInfos.size() &&
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"Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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@ -292,7 +294,8 @@ void ExecutionDomainFix::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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int MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number.");
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assert(MBBNumber < MBBOutRegsInfos.size() &&
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"Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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for (DomainValue *OldLiveReg : MBBOutRegsInfos[MBBNumber]) {
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release(OldLiveReg);
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@ -314,8 +317,8 @@ bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
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return !DomP.first;
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}
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bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI,
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unsigned OpIdx, unsigned Pref) {
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bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref) {
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MachineOperand &MO = MI->getOperand(OpIdx);
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assert(MO.isUndef() && "Expected undef machine operand");
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@ -388,8 +391,8 @@ void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
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assert(!MI->isDebugValue() && "Won't process debug values");
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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@ -410,11 +413,12 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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assert(!MI->isDebugValue() && "Won't process debug values");
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int MBBNumber = MI->getParent()->getNumber();
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assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
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assert(MBBNumber < MBBReachingDefs.size() &&
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"Unexpected basic block number.");
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.getReg())
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continue;
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@ -451,8 +455,8 @@ void BreakFalseDeps::processDefs(MachineInstr *MI) {
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.getReg())
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continue;
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@ -499,9 +503,11 @@ void BreakFalseDeps::processUndefReads(MachineBasicBlock *MBB) {
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void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
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// Collapse all uses.
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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e = mi->getDesc().getNumOperands();
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i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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force(rx, domain);
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}
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@ -510,7 +516,8 @@ void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
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// Kill all defs and force them.
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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kill(rx);
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force(rx, domain);
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@ -527,9 +534,11 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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SmallVector<int, 4> used;
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if (!LiveRegs.empty())
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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e = mi->getDesc().getNumOperands();
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i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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DomainValue *dv = LiveRegs[rx];
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if (dv == nullptr)
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@ -541,7 +550,8 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// Restrict available domains to the ones in common with the operand.
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// If there are no common domains, we must pay the cross-domain
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// penalty for this operand.
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if (common) available = common;
|
||||
if (common)
|
||||
available = common;
|
||||
} else if (common)
|
||||
// Open DomainValue is compatible, save it for merging.
|
||||
used.push_back(rx);
|
||||
@ -573,11 +583,11 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
|
||||
}
|
||||
// Sorted insertion.
|
||||
// Enables giving priority to the latest domains during merging.
|
||||
auto I = std::upper_bound(Regs.begin(), Regs.end(), rx,
|
||||
[&](int LHS, const int RHS) {
|
||||
return RDA->getReachingDef(mi, RC->getRegister(LHS)) <
|
||||
RDA->getReachingDef(mi, RC->getRegister(RHS));
|
||||
});
|
||||
auto I = std::upper_bound(
|
||||
Regs.begin(), Regs.end(), rx, [&](int LHS, const int RHS) {
|
||||
return RDA->getReachingDef(mi, RC->getRegister(LHS)) <
|
||||
RDA->getReachingDef(mi, RC->getRegister(RHS));
|
||||
});
|
||||
Regs.insert(I, rx);
|
||||
}
|
||||
|
||||
@ -618,7 +628,8 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
|
||||
// Finally set all defs and non-collapsed uses to dv. We must iterate through
|
||||
// all the operators, including imp-def ones.
|
||||
for (MachineOperand &mo : mi->operands()) {
|
||||
if (!mo.isReg()) continue;
|
||||
if (!mo.isReg())
|
||||
continue;
|
||||
for (int rx : regIndices(mo.getReg())) {
|
||||
if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
|
||||
kill(rx);
|
||||
@ -656,7 +667,7 @@ void ReachingDefAnalysis::processBasicBlock(
|
||||
leaveBasicBlock(TraversedMBB);
|
||||
}
|
||||
|
||||
void BreakFalseDeps::processBasicBlock(MachineBasicBlock* MBB) {
|
||||
void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB) {
|
||||
UndefReads.clear();
|
||||
// If this block is not done, it makes little sense to make any decisions
|
||||
// based on clearance information. We need to make a second pass anyway,
|
||||
@ -673,17 +684,17 @@ bool LoopTraversal::isBlockDone(MachineBasicBlock *MBB) {
|
||||
int MBBNumber = MBB->getNumber();
|
||||
assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number.");
|
||||
return MBBInfos[MBBNumber].PrimaryCompleted &&
|
||||
MBBInfos[MBBNumber].IncomingCompleted == MBBInfos[MBBNumber].PrimaryIncoming &&
|
||||
MBBInfos[MBBNumber].IncomingCompleted ==
|
||||
MBBInfos[MBBNumber].PrimaryIncoming &&
|
||||
MBBInfos[MBBNumber].IncomingProcessed == MBB->pred_size();
|
||||
}
|
||||
|
||||
LoopTraversal::TraversalOrder
|
||||
LoopTraversal::traverse(MachineFunction &MF) {
|
||||
LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) {
|
||||
// Initialize the MMBInfos
|
||||
MBBInfos.assign(MF.getNumBlockIDs(), MBBInfo());
|
||||
|
||||
MachineBasicBlock *Entry = &*MF.begin();
|
||||
ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
|
||||
ReversePostOrderTraversal<MachineBasicBlock *> RPOT(Entry);
|
||||
SmallVector<MachineBasicBlock *, 4> Workqueue;
|
||||
SmallVector<TraversedMBBInfo, 4> MBBTraversalOrder;
|
||||
for (MachineBasicBlock *MBB : RPOT) {
|
||||
@ -702,7 +713,8 @@ LoopTraversal::traverse(MachineFunction &MF) {
|
||||
MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done));
|
||||
for (MachineBasicBlock *Succ : ActiveMBB->successors()) {
|
||||
int SuccNumber = Succ->getNumber();
|
||||
assert(SuccNumber < MBBInfos.size() && "Unexpected basic block number.");
|
||||
assert(SuccNumber < MBBInfos.size() &&
|
||||
"Unexpected basic block number.");
|
||||
if (!isBlockDone(Succ)) {
|
||||
if (Primary)
|
||||
MBBInfos[SuccNumber].IncomingProcessed++;
|
||||
@ -722,8 +734,8 @@ LoopTraversal::traverse(MachineFunction &MF) {
|
||||
for (MachineBasicBlock *MBB : RPOT) {
|
||||
if (!isBlockDone(MBB))
|
||||
MBBTraversalOrder.push_back(TraversedMBBInfo(MBB, false, true));
|
||||
// Don't update successors here. We'll get to them anyway through this
|
||||
// loop.
|
||||
// Don't update successors here. We'll get to them anyway through this
|
||||
// loop.
|
||||
}
|
||||
|
||||
MBBInfos.clear();
|
||||
@ -753,7 +765,8 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!anyregs) return false;
|
||||
if (!anyregs)
|
||||
return false;
|
||||
|
||||
RDA = &getAnalysis<ReachingDefAnalysis>();
|
||||
|
||||
@ -763,8 +776,8 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
|
||||
// therefore the LiveRegs array.
|
||||
AliasMap.resize(TRI->getNumRegs());
|
||||
for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
|
||||
for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
|
||||
AI.isValid(); ++AI)
|
||||
for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();
|
||||
++AI)
|
||||
AliasMap[*AI].push_back(i);
|
||||
}
|
||||
|
||||
@ -778,7 +791,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
|
||||
processBasicBlock(TraversedMBB);
|
||||
}
|
||||
|
||||
for (LiveRegsDVInfo OutLiveRegs: MBBOutRegsInfos) {
|
||||
for (LiveRegsDVInfo OutLiveRegs : MBBOutRegsInfos) {
|
||||
for (DomainValue *OutLiveReg : OutLiveRegs) {
|
||||
if (OutLiveReg)
|
||||
release(OutLiveReg);
|
||||
@ -856,7 +869,8 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
|
||||
int InstId = InstIds[MI];
|
||||
int DefRes = ReachingDedDefaultVal;
|
||||
int MBBNumber = MI->getParent()->getNumber();
|
||||
assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number.");
|
||||
assert(MBBNumber < MBBReachingDefs.size() &&
|
||||
"Unexpected basic block number.");
|
||||
int LatestDef = ReachingDedDefaultVal;
|
||||
for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
|
||||
for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user