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Drop <def,dead> flags when merging into an unused lane.

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The new coalescer can merge a dead def into an unused lane of an
otherwise live vector register.

Clear the <dead> flag when that happens since the flag refers to the
full virtual register which is still live after the partial dead def.

This fixes PR14079.

llvm-svn: 165877
This commit is contained in:
Jakob Stoklund Olesen 2012-10-13 17:26:47 +00:00
parent 7fafebf1b4
commit 4aac24404c
2 changed files with 36 additions and 5 deletions
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13
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -1739,15 +1739,20 @@ void JoinVals::pruneValues(JoinVals &Other,
// has been replaced.
Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
bool EraseImpDef = OtherV.IsImplicitDef && OtherV.Resolution == CR_Keep;
if (!EraseImpDef && !Def.isBlock()) {
if (!Def.isBlock()) {
// Remove <def,read-undef> flags. This def is now a partial redef.
// Also remove <def,dead> flags since the joined live range will
// continue past this instruction.
for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
MO.isValid(); ++MO)
if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg)
MO->setIsUndef(false);
if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
MO->setIsUndef(EraseImpDef);
MO->setIsDead(false);
}
// This value will reach instructions below, but we need to make sure
// the live range also reaches the instruction at Def.
EndPoints.push_back(Def);
if (!EraseImpDef)
EndPoints.push_back(Def);
}
DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
<< ": " << Other.LI << '\n');

28
test/CodeGen/ARM/coalesce-subregs.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing | FileCheck %s
; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing -verify-machineinstrs | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios0.0.0"
@ -263,3 +263,29 @@ bb31: ; preds = %bb12, %bb
declare <2 x float> @baz(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
declare <2 x float> @baz67(<2 x float>, <2 x float>) nounwind readnone
%struct.wombat.5 = type { %struct.quux, %struct.quux, %struct.quux, %struct.quux }
%struct.quux = type { <4 x float> }
; CHECK: pr14079
define linkonce_odr arm_aapcs_vfpcc %struct.wombat.5 @pr14079(i8* nocapture %arg, i8* nocapture %arg1, i8* nocapture %arg2) nounwind uwtable inlinehint {
bb:
%tmp = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp3 = bitcast <1 x i64> %tmp to <2 x float>
%tmp4 = shufflevector <2 x float> %tmp3, <2 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
%tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <2 x i32> <i32 1, i32 3>
%tmp6 = bitcast <2 x float> %tmp5 to <1 x i64>
%tmp7 = shufflevector <1 x i64> undef, <1 x i64> %tmp6, <2 x i32> <i32 0, i32 1>
%tmp8 = bitcast <2 x i64> %tmp7 to <4 x float>
%tmp9 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> <i32 1>
%tmp10 = bitcast <1 x i64> %tmp9 to <2 x float>
%tmp11 = shufflevector <2 x float> %tmp10, <2 x float> undef, <2 x i32> <i32 0, i32 2>
%tmp12 = shufflevector <2 x float> %tmp11, <2 x float> undef, <2 x i32> <i32 0, i32 2>
%tmp13 = bitcast <2 x float> %tmp12 to <1 x i64>
%tmp14 = shufflevector <1 x i64> %tmp13, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%tmp15 = bitcast <2 x i64> %tmp14 to <4 x float>
%tmp16 = insertvalue %struct.wombat.5 undef, <4 x float> %tmp8, 1, 0
%tmp17 = insertvalue %struct.wombat.5 %tmp16, <4 x float> %tmp15, 2, 0
%tmp18 = insertvalue %struct.wombat.5 %tmp17, <4 x float> undef, 3, 0
ret %struct.wombat.5 %tmp18
}