RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-05 18:49:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

AArch64: only try to get operand of a known node.

Browse Source 
A bug in r216725 meant we tried to discover the type of a SETCC before
confirming the node actually was a SETCC.

llvm-svn: 216734
This commit is contained in:
Tim Northover 2014-08-29 15:34:58 +00:00
parent 84a20ba17d
commit 4af4565d10
2 changed files with 12 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7994,18 +7994,18 @@ static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) { static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
EVT ResVT = N->getValueType(0); EVT ResVT = N->getValueType(0);
EVT SrcVT = N0.getOperand(0).getValueType();
int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits(); if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
return SDValue();
// If NumMaskElts == 0, the comparison is larger than select result. The // If NumMaskElts == 0, the comparison is larger than select result. The
// largest real NEON comparison is 64-bits per lane, which means the result is // largest real NEON comparison is 64-bits per lane, which means the result is
// at most 32-bits and an illegal vector. Just bail out for now. // at most 32-bits and an illegal vector. Just bail out for now.
EVT SrcVT = N0.getOperand(0).getValueType();
int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
if (!ResVT.isVector() || NumMaskElts == 0) if (!ResVT.isVector() || NumMaskElts == 0)
return SDValue(); return SDValue();
if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
return SDValue();
SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts); SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
EVT CCVT = SrcVT.changeVectorElementTypeToInteger(); EVT CCVT = SrcVT.changeVectorElementTypeToInteger();

7
test/CodeGen/AArch64/cond-sel.ll
View File

@ -224,3 +224,10 @@ define <1 x i1> @test_wide_comparison(i32 %in) {
%res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer %res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer
ret <1 x i1> %res ret <1 x i1> %res
} }
define i32 @test_select_undef() {
; CHECK-LABEL: test_select_undef:
; CHECK: ret
%res = select i1 undef, i32 0, i32 42
ret i32 %res
}