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* Minor cleanups

Browse Source 
* Reduce number of #includes
* Remove blatently misleading qualifiers (how do you have an inlined pure virtual function?)
* Remove unnecesary & ignored qualifiers (const int argument vs int argument)
* SparcInternals.h now no longer #includes RegClass.h or SparcRegClassInfo.h
* Pull inlined functions out of .h file if they are virtual and interfere with dependencies

llvm-svn: 1677
This commit is contained in:
Chris Lattner 2002-02-04 05:59:25 +00:00
parent cfc28e1cce
commit 4c0bf66bdd
5 changed files with 350 additions and 538 deletions
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1
lib/Target/Sparc/Sparc.cpp
View File

@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Method.h"
#include "llvm/PassManager.h"
#include <iostream>

260
lib/Target/Sparc/SparcInternals.h
View File

@ -12,14 +12,12 @@
#ifndef SPARC_INTERNALS_H
#define SPARC_INTERNALS_H
#include "SparcRegClassInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/MachineSchedInfo.h"
#include "llvm/Target/MachineFrameInfo.h"
#include "llvm/Target/MachineCacheInfo.h"
#include "llvm/CodeGen/RegClass.h"
#include "llvm/Target/MachineRegInfo.h"
#include "llvm/Type.h"
#include <sys/types.h>
@ -164,8 +162,6 @@ public:
Value* src,
Instruction* dest,
std::vector<MachineInstr*>& minstr) const;
};
@ -176,10 +172,7 @@ public:
//
//----------------------------------------------------------------------------
class UltraSparcRegInfo : public MachineRegInfo
{
private:
class UltraSparcRegInfo : public MachineRegInfo {
// The actual register classes in the Sparc
//
enum RegClassIDs {
@ -231,16 +224,18 @@ class UltraSparcRegInfo : public MachineRegInfo
// method args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation.
//
void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
const MachineInstr *MI,AddedInstrMapType &AIMap)const;
void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
const MachineInstr *MI,
std::hash_map<const MachineInstr *,
AddedInstrns *> &AIMap) const;
MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
unsigned RegClassID) const ;
MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
unsigned RegClassID) const;
void suggestReg4RetAddr(const MachineInstr * RetMI,
LiveRangeInfo& LRI) const;
void suggestReg4RetAddr(const MachineInstr *RetMI,
LiveRangeInfo &LRI) const;
void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
void suggestReg4CallAddr(const MachineInstr *CallMI, LiveRangeInfo &LRI,
std::vector<RegClass *> RCList) const;
@ -248,96 +243,29 @@ class UltraSparcRegInfo : public MachineRegInfo
// The following methods are used to find the addresses etc. contained
// in specail machine instructions like CALL/RET
//
Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
Value *getValue4ReturnAddr(const MachineInstr *MInst) const;
const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
// The following 3 methods are used to find the RegType (see enum above)
// of a LiveRange, Value and using the unified RegClassID
int getRegType(const LiveRange *const LR) const {
unsigned Typ;
switch( (LR->getRegClass())->getID() ) {
case IntRegClassID: return IntRegType;
case FloatRegClassID:
Typ = LR->getTypeID();
if( Typ == Type::FloatTyID )
return FPSingleRegType;
else if( Typ == Type::DoubleTyID )
return FPDoubleRegType;
else assert(0 && "Unknown type in FloatRegClass");
case IntCCRegClassID: return IntCCRegType;
case FloatCCRegClassID: return FloatCCRegType ;
default: assert( 0 && "Unknown reg class ID");
return 0;
}
}
int getRegType(const Value *const Val) const {
unsigned Typ;
switch( getRegClassIDOfValue(Val) ) {
case IntRegClassID: return IntRegType;
case FloatRegClassID:
Typ = (Val->getType())->getPrimitiveID();
if( Typ == Type::FloatTyID )
return FPSingleRegType;
else if( Typ == Type::DoubleTyID )
return FPDoubleRegType;
else assert(0 && "Unknown type in FloatRegClass");
case IntCCRegClassID: return IntCCRegType;
case FloatCCRegClassID: return FloatCCRegType ;
default: assert( 0 && "Unknown reg class ID");
return 0;
}
}
int getRegType(int reg) const {
if( reg < 32 )
return IntRegType;
else if ( reg < (32 + 32) )
return FPSingleRegType;
else if ( reg < (64 + 32) )
return FPDoubleRegType;
else if( reg < (64+32+4) )
return FloatCCRegType;
else if( reg < (64+32+4+2) )
return IntCCRegType;
else
assert(0 && "Invalid register number in getRegType");
}
int getRegType(const LiveRange *LR) const;
int getRegType(const Value *Val) const;
int getRegType(int reg) const;
// The following methods are used to generate copy instructions to move
// data between condition code registers
//
MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
// Used to generate a copy instruction based on the register class of
// value.
//
MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
const int RegType) const;
MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
int RegType) const;
// The following 2 methods are used to order the instructions addeed by
@ -358,53 +286,28 @@ class UltraSparcRegInfo : public MachineRegInfo
bool isVarArgCall(const MachineInstr *CallMI) const;
public:
// constructor
//
UltraSparcRegInfo(const TargetMachine& tgt ) :
MachineRegInfo(tgt),
UltraSparcInfo(& (const UltraSparc&) tgt),
NumOfIntArgRegs(6),
NumOfFloatArgRegs(32),
InvalidRegNum(1000) {
MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
~UltraSparcRegInfo(void) { } // empty destructor
public:
UltraSparcRegInfo(const UltraSparc &tgt);
// To get complete machine information structure using the machine register
// information
//
inline const UltraSparc & getUltraSparcInfo() const {
inline const UltraSparc &getUltraSparcInfo() const {
return *UltraSparcInfo;
}
// To find the register class of a Value
//
inline unsigned getRegClassIDOfValue (const Value *const Val,
bool isCCReg = false) const {
Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
inline unsigned getRegClassIDOfValue(const Value *Val,
bool isCCReg = false) const {
Type::PrimitiveID ty = Val->getType()->getPrimitiveID();
unsigned res;
if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
(ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
res = IntRegClassID; // sparc int reg (ty=0: void)
else if( ty <= Type::DoubleTyID)
res = IntRegClassID; // sparc int reg (ty=0: void)
else if (ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
else {
std::cerr << "TypeID: " << ty << "\n";
@ -419,22 +322,21 @@ class UltraSparcRegInfo : public MachineRegInfo
}
// returns the register that contains always zero
// this is the unified register number
// getZeroRegNum - returns the register that contains always zero this is the
// unified register number
//
inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
virtual int getZeroRegNum() const;
// returns the reg used for pushing the address when a method is called.
// This can be used for other purposes between calls
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
unsigned getCallAddressReg() const;
// Returns the register containing the return address.
// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
unsigned getReturnAddressReg() const;
@ -442,32 +344,32 @@ class UltraSparcRegInfo : public MachineRegInfo
// method args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
//
void suggestRegs4MethodArgs(const Method *const Meth,
void suggestRegs4MethodArgs(const Method *Meth,
LiveRangeInfo& LRI) const;
void suggestRegs4CallArgs(const MachineInstr *const CallMI,
void suggestRegs4CallArgs(const MachineInstr *CallMI,
LiveRangeInfo& LRI,
std::vector<RegClass *> RCL) const;
void suggestReg4RetValue(const MachineInstr *const RetMI,
void suggestReg4RetValue(const MachineInstr *RetMI,
LiveRangeInfo& LRI) const;
void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
AddedInstrns *const FirstAI) const;
void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI,
AddedInstrns *FirstAI) const;
void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
AddedInstrns *const CallAI, PhyRegAlloc &PRA,
void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
AddedInstrns *CallAI, PhyRegAlloc &PRA,
const BasicBlock *BB) const;
void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
AddedInstrns *const RetAI) const;
void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
AddedInstrns *RetAI) const;
// method used for printing a register for debugging purposes
//
static void printReg(const LiveRange *const LR) ;
static void printReg(const LiveRange *LR);
// this method provides a unique number for each register
//
@ -491,36 +393,7 @@ class UltraSparcRegInfo : public MachineRegInfo
// given the unified register number, this gives the name
// for generating assembly code or debugging.
//
inline const std::string getUnifiedRegName(int reg) const {
if( reg < 32 )
return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) )
return SparcFloatRegOrder::getRegName( reg - 32);
else if( reg < (64+32+4) )
return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
else if (reg== InvalidRegNum) //****** TODO: Remove */
return "<*NoReg*>";
else
assert(0 && "Invalid register number");
return "";
}
// The fllowing methods are used by instruction selection
//
inline unsigned getRegNumInCallersWindow(int reg) {
if (reg == InvalidRegNum || reg >= 32)
return reg;
return SparcIntRegOrder::getRegNumInCallersWindow(reg);
}
inline bool mustBeRemappedInCallersWindow(int reg) {
return (reg != InvalidRegNum && reg < 32);
}
virtual const std::string getUnifiedRegName(int reg) const;
// returns the # of bytes of stack space allocated for each register
@ -528,7 +401,7 @@ class UltraSparcRegInfo : public MachineRegInfo
// register types. We can optimize this later if necessary to save stack
// space (However, should make sure that stack alignment is correct)
//
inline int getSpilledRegSize(const int RegType) const {
inline int getSpilledRegSize(int RegType) const {
return 8;
}
@ -541,14 +414,14 @@ class UltraSparcRegInfo : public MachineRegInfo
// The following methods are used to generate "copy" machine instructions
// for an architecture.
//
MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
const int RegType) const;
MachineInstr * cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
int RegType) const;
MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
const int Offset, const int RegType) const;
MachineInstr * cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
int Offset, int RegType) const;
MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
const unsigned DestReg, const int RegType) const;
MachineInstr * cpMem2RegMI(unsigned SrcPtrReg, int Offset,
unsigned DestReg, int RegType) const;
MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
@ -556,30 +429,22 @@ class UltraSparcRegInfo : public MachineRegInfo
// To see whether a register is a volatile (i.e., whehter it must be
// preserved acorss calls)
//
inline bool isRegVolatile(const int RegClassID, const int Reg) const {
return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
inline bool isRegVolatile(int RegClassID, int Reg) const {
return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
}
inline unsigned getFramePointer() const {
return SparcIntRegOrder::i6;
}
virtual unsigned getFramePointer() const;
virtual unsigned getStackPointer() const;
inline unsigned getStackPointer() const {
return SparcIntRegOrder::o6;
}
inline int getInvalidRegNum() const {
virtual int getInvalidRegNum() const {
return InvalidRegNum;
}
// This method inserts the caller saving code for call instructions
//
void insertCallerSavingCode(const MachineInstr *MInst,
const BasicBlock *BB, PhyRegAlloc &PRA ) const;
};
@ -596,10 +461,9 @@ class UltraSparcRegInfo : public MachineRegInfo
class UltraSparcSchedInfo: public MachineSchedInfo {
public:
/*ctor*/ UltraSparcSchedInfo (const TargetMachine& tgt);
/*dtor*/ virtual ~UltraSparcSchedInfo () {}
UltraSparcSchedInfo(const TargetMachine &tgt);
protected:
virtual void initializeResources ();
virtual void initializeResources();
};
@ -614,7 +478,7 @@ protected:
class UltraSparcFrameInfo: public MachineFrameInfo {
public:
/*ctor*/ UltraSparcFrameInfo(const TargetMachine& tgt) : MachineFrameInfo(tgt) {}
UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
public:
int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}

90
lib/Target/Sparc/SparcRegClassInfo.cpp
View File

@ -1,4 +1,4 @@
#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "llvm/CodeGen/IGNode.h"
#include "llvm/Target/Sparc.h"
#include <iostream>
@ -17,23 +17,22 @@ using std::cerr;
// If both above fail, spill.
//
//-----------------------------------------------------------------------------
void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
{
LiveRange * LR = Node->getParentLR();
void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const {
LiveRange *LR = Node->getParentLR();
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
for (unsigned n=0; n < NumNeighbors; n++) { // for each neigh
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
if( NeighLR->hasColor() ) // if has a color
IsColorUsedArr[ NeighLR->getColor() ] = true; // record that color
if(NeighLR->hasColor()) // if has a color
IsColorUsedArr[NeighLR->getColor()] = true; // record that color
else if( NeighLR->hasSuggestedColor() ) {
else if (NeighLR->hasSuggestedColor()) {
// if the neighbout can use the suggested color
if( NeighLR-> isSuggestedColorUsable() )
IsColorUsedArr[ NeighLR->getSuggestedColor() ] = true;
// if the neighbout can use the suggested color
if(NeighLR->isSuggestedColorUsable())
IsColorUsedArr[NeighLR->getSuggestedColor()] = true;
}
}
@ -108,7 +107,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
}
if( ColorFound) {
if (ColorFound) {
LR->setColor(c);
// get the live range corresponding to live var
// since LR span across calls, must save across calls
@ -122,13 +121,8 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
// If we couldn't find a color regardless of call interference - i.e., we
// don't have either a volatile or non-volatile color left
//
if( !ColorFound )
if (!ColorFound)
LR->markForSpill(); // no color found - must spill
if( DEBUG_RA)
UltraSparcRegInfo::printReg( LR );
}
@ -213,10 +207,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
if( ColorFound >= 0 ) { // if we could find a color
LR->setColor(ColorFound);
if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
return;
}
else {
} else {
// if we didn't find a color becuase the LR was single precision or
// all f32-f63 range is filled, we try to allocate a register from
@ -241,7 +233,6 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
if( ColorFound >= 0 ) { // if we could find a color
LR->setColor(ColorFound);
if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
return;
}
else if( isCallInterf ) {
@ -260,63 +251,36 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
if( ColorFound >= 0 ) {
LR->setColor(ColorFound); // first color found in preffered order
LR->markForSaveAcrossCalls();
if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
return;
} else {
// we are here because no color could be found
LR->markForSpill(); // no color found - must spill
}
// we are here because no color could be found
LR->markForSpill(); // no color found - must spill
if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
}
//-----------------------------------------------------------------------------
// Helper method for coloring a node of Float Reg class.
// Finds the first available color in the range [Start,End] depending on the
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
int SparcFloatRegClass::findFloatColor(const LiveRange *const LR,
unsigned Start,
unsigned End,
bool IsColorUsedArr[] ) const {
int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
unsigned Start, unsigned End,
bool IsColorUsedArr[] ) const {
bool ColorFound = false;
unsigned c;
if( LR->getTypeID() == Type::DoubleTyID ) {
if (LR->getTypeID() == Type::DoubleTyID) {
// find first unused color for a double
for( c=Start; c < End ;c+= 2){
if( ! IsColorUsedArr[ c ] && ! IsColorUsedArr[ c+1 ])
{ ColorFound=true; break; }
}
for (c=Start; c < End ; c+= 2)
if (!IsColorUsedArr[c] && !IsColorUsedArr[c+1])
return c;
} else {
// find first unused color for a single
for( c=Start; c < End; c++) {
if( ! IsColorUsedArr[ c ] ) { ColorFound=true; break; }
}
for (c = Start; c < End; c++)
if (!IsColorUsedArr[c])
return c;
}
if( ColorFound ) return c;
else return -1;
return -1;
}

139
lib/Target/Sparc/SparcRegClassInfo.h
View File

@ -17,34 +17,27 @@
// Int register names in same order as enum in class SparcIntRegOrder
static const std::string IntRegNames[] =
{
static const std::string IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"i0", "i1", "i2", "i3", "i4", "i5",
"i6", "i7",
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o6" };
"o6"
};
class SparcIntRegOrder{
public:
enum RegsInPrefOrder // colors possible for a LR (in preferred order)
{
struct SparcIntRegOrder {
enum RegsInPrefOrder { // colors possible for a LR (in preferred order)
// --- following colors are volatile across function calls
// %g0 can't be used for coloring - always 0
o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
// %o6 is sp,
// all %0's can get modified by a call
// --- following colors are NON-volatile across function calls
l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
@ -64,8 +57,7 @@ class SparcIntRegOrder{
// enumeration of %o0 (change StartOfAllRegs below)
// change isRegVloatile method below
// Also change IntRegNames above.
};
};
// max # of colors reg coloring can allocate
static unsigned int const NumOfAvailRegs = i6;
@ -75,41 +67,26 @@ class SparcIntRegOrder{
static unsigned int const NumOfAllRegs = o6 + 1;
static const std::string getRegName(const unsigned reg) {
static const std::string getRegName(unsigned reg) {
assert( reg < NumOfAllRegs );
return IntRegNames[reg];
}
static unsigned int getRegNumInCallersWindow(const unsigned reg) {
if (reg <= l7 || reg == o6) {
assert(0 && "registers o0-o7 and l0-l7 are not visible in caller");
return reg;
}
if (reg <= i7)
return reg - (i0 - o0);
assert((reg >= g0 || reg <= g7) && "Unrecognized integer register number");
return reg;
}
};
class SparcIntRegClass : public MachineRegClassInfo
{
public:
struct SparcIntRegClass : public MachineRegClassInfo {
SparcIntRegClass(unsigned ID)
: MachineRegClassInfo(ID,
SparcIntRegOrder::NumOfAvailRegs,
SparcIntRegOrder::NumOfAllRegs)
{ }
SparcIntRegOrder::NumOfAllRegs) { }
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const;
inline bool isRegVolatile(const int Reg) const {
inline bool isRegVolatile(int Reg) const {
return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
}
};
@ -157,37 +134,27 @@ class SparcFloatRegOrder{
static unsigned int const StartOfAllRegs = f0;
static const std::string getRegName(const unsigned reg) {
assert( reg < NumOfAllRegs );
static const std::string getRegName(unsigned reg) {
assert (reg < NumOfAllRegs);
return FloatRegNames[reg];
}
};
class SparcFloatRegClass : public MachineRegClassInfo
{
private:
int findFloatColor(const LiveRange *const LR, unsigned Start,
unsigned End, bool IsColorUsedArr[] ) const;
public:
class SparcFloatRegClass : public MachineRegClassInfo {
int findFloatColor(const LiveRange *LR, unsigned Start,
unsigned End, bool IsColorUsedArr[]) const;
public:
SparcFloatRegClass(unsigned ID)
: MachineRegClassInfo(ID,
SparcFloatRegOrder::NumOfAvailRegs,
SparcFloatRegOrder::NumOfAllRegs)
{ }
SparcFloatRegOrder::NumOfAllRegs) {}
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const;
// according to Sparc 64 ABI, all %fp regs are volatile
inline bool isRegVolatile(const int Reg) const { return true; }
inline bool isRegVolatile(int Reg) const { return true; }
};
@ -203,44 +170,35 @@ class SparcFloatRegClass : public MachineRegClassInfo
//-----------------------------------------------------------------------------
static const std::string IntCCRegNames[] =
{
"xcc", "ccr"
};
static const std::string IntCCRegNames[] = {
"xcc", "ccr"
};
class SparcIntCCRegOrder{
public:
struct SparcIntCCRegOrder {
enum RegsInPrefOrder {
xcc, ccr // only one is available - see the note above
};
static const std::string getRegName(const unsigned reg) {
assert( reg < 2 );
static const std::string getRegName(unsigned reg) {
assert(reg < 2);
return IntCCRegNames[reg];
}
};
class SparcIntCCRegClass : public MachineRegClassInfo
{
public:
struct SparcIntCCRegClass : public MachineRegClassInfo {
SparcIntCCRegClass(unsigned ID)
: MachineRegClassInfo(ID, 1, 2) { }
inline void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
inline void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const {
Node->setColor(0); // only one int cc reg is available
}
// according to Sparc 64 ABI, %ccr is volatile
//
inline bool isRegVolatile(const int Reg) const { return true; }
inline bool isRegVolatile(int Reg) const { return true; }
};
@ -252,54 +210,35 @@ public:
// Only 4 Float CC registers are available
//-----------------------------------------------------------------------------
static const std::string FloatCCRegNames[] = {
"fcc0", "fcc1", "fcc2", "fcc3"
};
static const std::string FloatCCRegNames[] =
{
"fcc0", "fcc1", "fcc2", "fcc3"
};
class SparcFloatCCRegOrder{
public:
struct SparcFloatCCRegOrder{
enum RegsInPrefOrder {
fcc0, fcc1, fcc2, fcc3
};
static const std::string getRegName(const unsigned reg) {
assert( reg < 4 );
static const std::string getRegName(unsigned reg) {
assert (reg < 4);
return FloatCCRegNames[reg];
}
};
class SparcFloatCCRegClass : public MachineRegClassInfo
{
public:
struct SparcFloatCCRegClass : public MachineRegClassInfo {
SparcFloatCCRegClass(unsigned ID)
: MachineRegClassInfo(ID, 4, 4) { }
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const {
int c;
for(c=0; c < 4 && IsColorUsedArr[c] ; ++c) ; // find color
assert( (c < 4) && "Can allocate only 4 float cc registers");
assert ((c < 4) && "Can allocate only 4 float cc registers");
Node->setColor(c);
}
// according to Sparc 64 ABI, all %fp CC regs are volatile
//
inline bool isRegVolatile(const int Reg) const { return true; }
inline bool isRegVolatile(int Reg) const { return true; }
};
#endif

398
lib/Target/Sparc/SparcRegInfo.cpp
View File

@ -5,18 +5,83 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/Sparc.h"
#include "SparcInternals.h"
#include "llvm/Method.h"
#include "llvm/iTerminators.h"
#include "llvm/iOther.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "SparcRegClassInfo.h"
#include "llvm/Target/Sparc.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Analysis/LiveVar/LiveVarSet.h"
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
#include "llvm/iTerminators.h"
#include "llvm/iOther.h"
#include "llvm/DerivedTypes.h"
#include <iostream>
using std::cerr;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
// getZeroRegNum - returns the register that contains always zero this is the
// unified register number
//
int UltraSparcRegInfo::getZeroRegNum() const { return SparcIntRegOrder::g0; }
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
unsigned UltraSparcRegInfo::getCallAddressReg() const {
return SparcIntRegOrder::o7;
}
// Returns the register containing the return address.
// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned UltraSparcRegInfo::getReturnAddressReg() const {
return SparcIntRegOrder::i7;
}
// given the unified register number, this gives the name
// for generating assembly code or debugging.
//
const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
if( reg < 32 )
return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) )
return SparcFloatRegOrder::getRegName( reg - 32);
else if( reg < (64+32+4) )
return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
else if (reg== InvalidRegNum) //****** TODO: Remove */
return "<*NoReg*>";
else
assert(0 && "Invalid register number");
return "";
}
unsigned UltraSparcRegInfo::getFramePointer() const {
return SparcIntRegOrder::i6;
}
unsigned UltraSparcRegInfo::getStackPointer() const {
return SparcIntRegOrder::o6;
}
//---------------------------------------------------------------------------
// Finds the return value of a sparc specific call instruction
//---------------------------------------------------------------------------
@ -31,8 +96,8 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
// a CALL instr
//
if( NumOfImpRefs > 1 )
if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
return CallMI->getImplicitRef(NumOfImpRefs-2);
if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
return CallMI->getImplicitRef(NumOfImpRefs-2);
} else if (OpCode == JMPLCALL) {
@ -41,8 +106,7 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
if(NumOfImpRefs > 0)
if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
return CallMI->getImplicitRef(NumOfImpRefs-1);
}
else
} else
assert(0 && "OpCode must be CALL/JMPL for a call instr");
return NULL;
@ -54,81 +118,122 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
// Finds the return address of a call sparc specific call instruction
//---------------------------------------------------------------------------
const Value *
UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI)const {
UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI) const {
unsigned OpCode = CallMI->getOpCode();
if( OpCode == CALL) {
if (OpCode == CALL) {
unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
// The last implicit operand is the return address of a CALL instr
//
return CallMI->getImplicitRef(NumOfImpRefs-1);
return CallMI->getImplicitRef(NumOfImpRefs-1);
}
else if( OpCode == JMPLCALL ) {
MachineOperand & MO = ( MachineOperand &) CallMI->getOperand(2);
} else if(OpCode == JMPLCALL) {
MachineOperand &MO = (MachineOperand &)CallMI->getOperand(2);
return MO.getVRegValue();
}
else
assert(0 && "OpCode must be CALL/JMPL for a call instr");
assert(0 && "There must be a return addr for a call instr");
return NULL;
assert(0 && "OpCode must be CALL/JMPL for a call instr");
return 0;
}
// The following 3 methods are used to find the RegType (see enum above)
// of a LiveRange, Value and using the unified RegClassID
//
int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
unsigned Typ;
switch (LR->getRegClass()->getID()) {
case IntRegClassID: return IntRegType;
case FloatRegClassID:
Typ = LR->getTypeID();
if (Typ == Type::FloatTyID)
return FPSingleRegType;
else if (Typ == Type::DoubleTyID)
return FPDoubleRegType;
assert(0 && "Unknown type in FloatRegClass");
case IntCCRegClassID: return IntCCRegType;
case FloatCCRegClassID: return FloatCCRegType;
default: assert( 0 && "Unknown reg class ID");
return 0;
}
}
int UltraSparcRegInfo::getRegType(const Value *Val) const {
unsigned Typ;
switch (getRegClassIDOfValue(Val)) {
case IntRegClassID: return IntRegType;
case FloatRegClassID:
Typ = Val->getType()->getPrimitiveID();
if (Typ == Type::FloatTyID)
return FPSingleRegType;
else if (Typ == Type::DoubleTyID)
return FPDoubleRegType;
assert(0 && "Unknown type in FloatRegClass");
case IntCCRegClassID: return IntCCRegType;
case FloatCCRegClassID: return FloatCCRegType ;
default: assert(0 && "Unknown reg class ID");
return 0;
}
}
int UltraSparcRegInfo::getRegType(int reg) const {
if (reg < 32)
return IntRegType;
else if (reg < (32 + 32))
return FPSingleRegType;
else if (reg < (64 + 32))
return FPDoubleRegType;
else if (reg < (64+32+4))
return FloatCCRegType;
else if (reg < (64+32+4+2))
return IntCCRegType;
else
assert(0 && "Invalid register number in getRegType");
}
//---------------------------------------------------------------------------
// Finds the # of actual arguments of the call instruction
//---------------------------------------------------------------------------
const unsigned
unsigned
UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
unsigned OpCode = CallMI->getOpCode();
unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
int NumArgs = -1;
if( OpCode == CALL ) {
switch( NumOfImpRefs ) {
unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
if (OpCode == CALL) {
switch (NumOfImpRefs) {
case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
case 1: NumArgs = 0;
break;
case 1: return 0;
default: // two or more implicit refs
if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
NumArgs = NumOfImpRefs - 2; // i.e., NumOfImpRef-2 is the ret val
if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
return NumOfImpRefs - 2;
else
NumArgs = NumOfImpRefs - 1;
return NumOfImpRefs - 1;
}
}
else if( OpCode == JMPLCALL ) {
} else if (OpCode == JMPLCALL) {
// The last implicit operand is the return value of a JMPL instr
if( NumOfImpRefs > 0 ) {
if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
NumArgs = NumOfImpRefs - 1; // i.e., NumOfImpRef-1 is the ret val
if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
return NumOfImpRefs - 1;
else
NumArgs = NumOfImpRefs;
return NumOfImpRefs;
}
else
NumArgs = NumOfImpRefs;
return NumOfImpRefs;
}
else
assert(0 && "OpCode must be CALL/JMPL for a call instr");
assert( (NumArgs != -1) && "Internal error in getCallInstNumArgs" );
return (unsigned) NumArgs;
assert(0 && "OpCode must be CALL/JMPL for a call instr");
return 0;
}
@ -156,7 +261,7 @@ bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI,
void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert( (RetMI->getNumOperands() >= 2)
@ -215,7 +320,7 @@ void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *Meth,
LiveRangeInfo& LRI) const
{
@ -264,9 +369,9 @@ void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
LiveRangeInfo& LRI,
AddedInstrns *const FirstAI) const {
void UltraSparcRegInfo::colorMethodArgs(const Method *Meth,
LiveRangeInfo &LRI,
AddedInstrns *FirstAI) const {
// get the argument list
const Method::ArgumentListType& ArgList = Meth->getArgumentList();
@ -394,12 +499,11 @@ void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
//---------------------------------------------------------------------------
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
LiveRangeInfo& LRI,
std::vector<RegClass *> RCList) const {
@ -422,19 +526,16 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
const Value *RetVal = getCallInstRetVal( CallMI );
if( RetVal ) {
assert( (! LRI.getLiveRangeForValue( RetVal ) ) &&
if (RetVal) {
assert ((!LRI.getLiveRangeForValue(RetVal)) &&
"LR for ret Value of call already definded!");
// create a new LR for the return value
LiveRange * RetValLR = new LiveRange();
RetValLR->add( RetVal );
unsigned RegClassID = getRegClassIDOfValue( RetVal );
RetValLR->setRegClass( RCList[RegClassID] );
LRI.addLRToMap( RetVal, RetValLR);
// create a new LR for the return value
LiveRange *RetValLR = new LiveRange();
RetValLR->add(RetVal);
unsigned RegClassID = getRegClassIDOfValue(RetVal);
RetValLR->setRegClass(RCList[RegClassID]);
LRI.addLRToMap(RetVal, RetValLR);
// now suggest a register depending on the register class of ret arg
@ -443,7 +544,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
else if (RegClassID == FloatRegClassID )
RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
@ -469,7 +569,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
printValue(CallArg); cerr << "\n";
}
assert(0 && "NO LR for call arg");
// continue;
}
unsigned RegType = getRegType( LR );
@ -504,9 +603,9 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
// to instert copy instructions.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
LiveRangeInfo& LRI,
AddedInstrns *const CallAI,
void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
LiveRangeInfo &LRI,
AddedInstrns *CallAI,
PhyRegAlloc &PRA,
const BasicBlock *BB) const {
@ -666,9 +765,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
}
if( LR->hasColor() ) {
if (LR->hasColor()) {
unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
// if LR received the correct color, nothing to do
@ -707,9 +804,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
AddedInstrnsBefore.push_back( AdMI );
}
}
else {
} else {
// Now, we have to pass the arg on stack. Since LR received a register
// we just have to move that register to the stack position where
// the argument must be passed
@ -727,9 +822,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
}
}
else { // LR is not colored (i.e., spilled)
} else { // LR is not colored (i.e., spilled)
if( isArgInReg ) {
@ -792,18 +885,16 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
}
}
} // for each parameter in call instruction
// if we added any instruction before the call instruction, verify
// that they are in the proper order and if not, reorder them
if( ! AddedInstrnsBefore.empty() ) {
if (!AddedInstrnsBefore.empty()) {
if( DEBUG_RA ) {
if (DEBUG_RA) {
cerr << "\nCalling reorder with instrns: \n";
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
cerr << *(AddedInstrnsBefore[i]);
@ -812,10 +903,10 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
std::vector<MachineInstr *> TmpVec;
OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
if( DEBUG_RA ) {
if (DEBUG_RA) {
cerr << "\nAfter reordering instrns: \n";
for(unsigned i=0; i < TmpVec.size(); i++)
cerr << *(TmpVec[i]);
for(unsigned i = 0; i < TmpVec.size(); i++)
cerr << *TmpVec[i];
}
// copy the results back from TmpVec to InstrnsBefore
@ -828,19 +919,16 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
//
insertCallerSavingCode(CallMI, BB, PRA);
// Reset optional args area again to be safe
PRA.mcInfo.resetOptionalArgs(target);
}
//---------------------------------------------------------------------------
// This method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
LiveRangeInfo& LRI) const {
void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
LiveRangeInfo &LRI) const {
assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
@ -864,14 +952,11 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
unsigned RegClassID = (LR->getRegClass())->getID();
if( RegClassID == IntRegClassID )
if (RegClassID == IntRegClassID)
LR->setSuggestedColor(SparcIntRegOrder::i0);
else if ( RegClassID == FloatRegClassID )
else if (RegClassID == FloatRegClassID)
LR->setSuggestedColor(SparcFloatRegOrder::f0);
}
}
@ -882,19 +967,19 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
// have to put a load instruction.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
LiveRangeInfo& LRI,
AddedInstrns *const RetAI) const {
void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
LiveRangeInfo &LRI,
AddedInstrns *RetAI) const {
assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
// if there is an implicit ref, that has to be the ret value
if( RetMI->getNumImplicitRefs() > 0 ) {
if(RetMI->getNumImplicitRefs() > 0) {
// The first implicit operand is the return value of a return instr
const Value *RetVal = RetMI->getImplicitRef(0);
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
if( ! LR ) {
cerr << "\nNo LR for:";
@ -913,19 +998,18 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
else if(RegClassID == FloatRegClassID)
CorrectCol = SparcFloatRegOrder::f0;
else {
assert( 0 && "Unknown RegClass");
assert (0 && "Unknown RegClass");
return;
}
// if the LR received the correct color, NOTHING to do
if( LR->hasColor() )
if( LR->getColor() == CorrectCol )
return;
if (LR->hasColor() && LR->getColor() == CorrectCol)
return;
unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol );
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
if( LR->hasColor() ) {
if (LR->hasColor()) {
// We are here because the LR was allocted a regiter
// It may be the suggested register or not
@ -956,9 +1040,8 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
// register number
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
const unsigned DestReg,
const int RegType) const {
MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
int RegType) const {
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
"Invalid Register");
@ -1002,16 +1085,11 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
const unsigned DestPtrReg,
const int Offset,
const int RegType) const {
MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
unsigned DestPtrReg,
int Offset, int RegType) const {
MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
case FloatCCRegType:
MI = new MachineInstr(STX, 3);
@ -1054,15 +1132,12 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
const int Offset,
const unsigned DestReg,
const int RegType) const {
MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
int Offset,
unsigned DestReg,
int RegType) const {
MachineInstr * MI = NULL;
switch( RegType ) {
switch (RegType) {
case IntRegType:
case FloatCCRegType:
MI = new MachineInstr(LDX, 3);
@ -1109,8 +1184,7 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
int RegType = getRegType( Src );
assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
@ -1118,9 +1192,7 @@ MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
MI = new MachineInstr(ADD, 3);
MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
@ -1185,12 +1257,11 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
const Value *RetVal = getCallInstRetVal( MInst );
if( RetVal ) {
if (RetVal) {
LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
assert( RetValLR && "No LR for RetValue of call");
assert(RetValLR && "No LR for RetValue of call");
if( RetValLR->hasColor())
if (RetValLR->hasColor())
PushedRegSet.insert(
getUnifiedRegNum((RetValLR->getRegClass())->getID(),
RetValLR->getColor() ) );
@ -1198,7 +1269,6 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
const LiveVarSet *LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
LiveVarSet::const_iterator LIt = LVSetAft->begin();
// for each live var in live variable set after machine inst
@ -1345,13 +1415,10 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
// number.
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
MachineInstr * MI = NULL;
MI = new MachineInstr(RDCCR, 2);
MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
MachineInstr * MI = new MachineInstr(RDCCR, 2);
MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
MI->SetMachineOperand(1, IntReg, true);
return MI;
}
@ -1360,14 +1427,11 @@ MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
// number.
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
MachineInstr * MI = NULL;
MI = new MachineInstr(WRCCR, 3);
MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
MachineInstr *MI = new MachineInstr(WRCCR, 3);
MI->SetMachineOperand(0, IntReg, false);
MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
return MI;
}
@ -1378,13 +1442,11 @@ MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
// Print the register assigned to a LR
//---------------------------------------------------------------------------
void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
unsigned RegClassID = (LR->getRegClass())->getID();
cerr << " *Node " << (LR->getUserIGNode())->getIndex();
if( ! LR->hasColor() ) {
if (!LR->hasColor()) {
cerr << " - could not find a color\n";
return;
}
@ -1393,10 +1455,10 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
cerr << " colored with color "<< LR->getColor();
if( RegClassID == IntRegClassID ) {
if (RegClassID == IntRegClassID) {
cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
} else if ( RegClassID == FloatRegClassID) {
} else if (RegClassID == FloatRegClassID) {
cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
if( LR->getTypeID() == Type::DoubleTyID )
cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
@ -1457,14 +1519,11 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
*/
bool CouldMoveAll;
bool DebugPrint = false;
do {
CouldMoveAll = true;
std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
for( ; DefIt != UnordVec.end(); ++DefIt ) {
@ -1496,8 +1555,6 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
if( UseInst == NULL) continue;
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
if( ! UseOp.opIsDef() &&
@ -1543,28 +1600,22 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
} // for all instructions in the UnordVec
} while( !CouldMoveAll);
} while(!CouldMoveAll);
if(DebugPrint) {
if (DebugPrint) {
cerr << "\nAdded instructions were reordered to:\n";
for(unsigned int i=0; i < OrdVec.size(); i++)
cerr << *(OrdVec[i]);
}
}
void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
MachineInstr *UnordInst,
PhyRegAlloc &PRA ) const {
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
if( ! UseOp.opIsDef() &&
@ -1642,7 +1693,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
} // for each instr in OrdVec
if( !DefEqUse ) {
if(!DefEqUse) {
// We didn't find a def in the OrdVec, so just append this inst
OrdVec.push_back( UnordInst );
@ -1650,11 +1701,4 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
}
}// if the operand in UnordInst is a use
}