mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-06 03:08:43 +00:00
* Minor cleanups
* Reduce number of #includes * Remove blatently misleading qualifiers (how do you have an inlined pure virtual function?) * Remove unnecesary & ignored qualifiers (const int argument vs int argument) * SparcInternals.h now no longer #includes RegClass.h or SparcRegClassInfo.h * Pull inlined functions out of .h file if they are virtual and interfere with dependencies llvm-svn: 1677
This commit is contained in:
Chris Lattner
parent
cfc28e1cce
commit
4c0bf66bdd
@ -17,6 +17,7 @@
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Method.h"
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#include "llvm/PassManager.h"
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#include <iostream>
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@ -12,14 +12,12 @@
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "SparcRegClassInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineSchedInfo.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/CodeGen/RegClass.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/Type.h"
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#include <sys/types.h>
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@ -164,8 +162,6 @@ public:
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& minstr) const;
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};
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@ -176,10 +172,7 @@ public:
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//
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//----------------------------------------------------------------------------
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class UltraSparcRegInfo : public MachineRegInfo
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{
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private:
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class UltraSparcRegInfo : public MachineRegInfo {
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// The actual register classes in the Sparc
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//
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enum RegClassIDs {
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@ -231,10 +224,12 @@ class UltraSparcRegInfo : public MachineRegInfo
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// method args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation.
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//
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void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
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const MachineInstr *MI,AddedInstrMapType &AIMap)const;
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void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
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const MachineInstr *MI,
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std::hash_map<const MachineInstr *,
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AddedInstrns *> &AIMap) const;
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MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
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MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
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unsigned RegClassID) const;
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void suggestReg4RetAddr(const MachineInstr *RetMI,
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@ -250,94 +245,27 @@ class UltraSparcRegInfo : public MachineRegInfo
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//
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Value *getValue4ReturnAddr(const MachineInstr *MInst) const;
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const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
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const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
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unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
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// The following 3 methods are used to find the RegType (see enum above)
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// of a LiveRange, Value and using the unified RegClassID
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int getRegType(const LiveRange *const LR) const {
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unsigned Typ;
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switch( (LR->getRegClass())->getID() ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = LR->getTypeID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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return 0;
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}
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}
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int getRegType(const Value *const Val) const {
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unsigned Typ;
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switch( getRegClassIDOfValue(Val) ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = (Val->getType())->getPrimitiveID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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return 0;
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}
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}
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int getRegType(int reg) const {
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if( reg < 32 )
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return IntRegType;
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else if ( reg < (32 + 32) )
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return FPSingleRegType;
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else if ( reg < (64 + 32) )
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return FPDoubleRegType;
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else if( reg < (64+32+4) )
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return FloatCCRegType;
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else if( reg < (64+32+4+2) )
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return IntCCRegType;
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else
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assert(0 && "Invalid register number in getRegType");
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}
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int getRegType(const LiveRange *LR) const;
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int getRegType(const Value *Val) const;
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int getRegType(int reg) const;
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// The following methods are used to generate copy instructions to move
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// data between condition code registers
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//
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MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
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MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
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MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
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MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
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// Used to generate a copy instruction based on the register class of
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// value.
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//
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MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
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const int RegType) const;
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MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
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int RegType) const;
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// The following 2 methods are used to order the instructions addeed by
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@ -358,31 +286,8 @@ class UltraSparcRegInfo : public MachineRegInfo
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bool isVarArgCall(const MachineInstr *CallMI) const;
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public:
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// constructor
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//
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UltraSparcRegInfo(const TargetMachine& tgt ) :
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MachineRegInfo(tgt),
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UltraSparcInfo(& (const UltraSparc&) tgt),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(32),
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InvalidRegNum(1000) {
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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}
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~UltraSparcRegInfo(void) { } // empty destructor
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UltraSparcRegInfo(const UltraSparc &tgt);
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// To get complete machine information structure using the machine register
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// information
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@ -391,14 +296,12 @@ class UltraSparcRegInfo : public MachineRegInfo
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return *UltraSparcInfo;
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}
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// To find the register class of a Value
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//
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inline unsigned getRegClassIDOfValue (const Value *const Val,
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inline unsigned getRegClassIDOfValue(const Value *Val,
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bool isCCReg = false) const {
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Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
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Type::PrimitiveID ty = Val->getType()->getPrimitiveID();
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unsigned res;
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if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
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@ -419,22 +322,21 @@ class UltraSparcRegInfo : public MachineRegInfo
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}
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// returns the register that contains always zero
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// this is the unified register number
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// getZeroRegNum - returns the register that contains always zero this is the
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// unified register number
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//
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inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
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virtual int getZeroRegNum() const;
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// returns the reg used for pushing the address when a method is called.
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// This can be used for other purposes between calls
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// getCallAddressReg - returns the reg used for pushing the address when a
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// method is called. This can be used for other purposes between calls
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//
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unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
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unsigned getCallAddressReg() const;
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// Returns the register containing the return address.
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// It should be made sure that this register contains the return
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// value when a return instruction is reached.
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//
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unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
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unsigned getReturnAddressReg() const;
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@ -442,32 +344,32 @@ class UltraSparcRegInfo : public MachineRegInfo
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// method args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation for Sparc.
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//
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void suggestRegs4MethodArgs(const Method *const Meth,
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void suggestRegs4MethodArgs(const Method *Meth,
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LiveRangeInfo& LRI) const;
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void suggestRegs4CallArgs(const MachineInstr *const CallMI,
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void suggestRegs4CallArgs(const MachineInstr *CallMI,
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LiveRangeInfo& LRI,
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std::vector<RegClass *> RCL) const;
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void suggestReg4RetValue(const MachineInstr *const RetMI,
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void suggestReg4RetValue(const MachineInstr *RetMI,
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LiveRangeInfo& LRI) const;
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void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
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AddedInstrns *const FirstAI) const;
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void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const;
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void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
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AddedInstrns *const CallAI, PhyRegAlloc &PRA,
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void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
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AddedInstrns *CallAI, PhyRegAlloc &PRA,
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const BasicBlock *BB) const;
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void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
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AddedInstrns *const RetAI) const;
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void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
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AddedInstrns *RetAI) const;
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// method used for printing a register for debugging purposes
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//
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static void printReg(const LiveRange *const LR) ;
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static void printReg(const LiveRange *LR);
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// this method provides a unique number for each register
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//
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@ -491,36 +393,7 @@ class UltraSparcRegInfo : public MachineRegInfo
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// given the unified register number, this gives the name
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// for generating assembly code or debugging.
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//
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inline const std::string getUnifiedRegName(int reg) const {
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if( reg < 32 )
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return SparcIntRegOrder::getRegName(reg);
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else if ( reg < (64 + 32) )
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return SparcFloatRegOrder::getRegName( reg - 32);
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else if( reg < (64+32+4) )
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return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
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else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
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return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
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else if (reg== InvalidRegNum) //****** TODO: Remove */
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return "<*NoReg*>";
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else
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assert(0 && "Invalid register number");
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return "";
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}
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// The fllowing methods are used by instruction selection
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//
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inline unsigned getRegNumInCallersWindow(int reg) {
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if (reg == InvalidRegNum || reg >= 32)
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return reg;
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return SparcIntRegOrder::getRegNumInCallersWindow(reg);
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}
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inline bool mustBeRemappedInCallersWindow(int reg) {
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return (reg != InvalidRegNum && reg < 32);
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}
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virtual const std::string getUnifiedRegName(int reg) const;
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// returns the # of bytes of stack space allocated for each register
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@ -528,7 +401,7 @@ class UltraSparcRegInfo : public MachineRegInfo
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// register types. We can optimize this later if necessary to save stack
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// space (However, should make sure that stack alignment is correct)
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//
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inline int getSpilledRegSize(const int RegType) const {
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inline int getSpilledRegSize(int RegType) const {
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return 8;
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}
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@ -541,14 +414,14 @@ class UltraSparcRegInfo : public MachineRegInfo
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// The following methods are used to generate "copy" machine instructions
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// for an architecture.
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//
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MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
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const int RegType) const;
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MachineInstr * cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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int RegType) const;
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MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
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const int Offset, const int RegType) const;
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MachineInstr * cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType) const;
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MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
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const unsigned DestReg, const int RegType) const;
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MachineInstr * cpMem2RegMI(unsigned SrcPtrReg, int Offset,
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unsigned DestReg, int RegType) const;
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MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
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@ -556,30 +429,22 @@ class UltraSparcRegInfo : public MachineRegInfo
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// To see whether a register is a volatile (i.e., whehter it must be
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// preserved acorss calls)
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//
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inline bool isRegVolatile(const int RegClassID, const int Reg) const {
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return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
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inline bool isRegVolatile(int RegClassID, int Reg) const {
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return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
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}
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inline unsigned getFramePointer() const {
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return SparcIntRegOrder::i6;
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}
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virtual unsigned getFramePointer() const;
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virtual unsigned getStackPointer() const;
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inline unsigned getStackPointer() const {
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return SparcIntRegOrder::o6;
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}
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inline int getInvalidRegNum() const {
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virtual int getInvalidRegNum() const {
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return InvalidRegNum;
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}
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// This method inserts the caller saving code for call instructions
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//
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void insertCallerSavingCode(const MachineInstr *MInst,
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const BasicBlock *BB, PhyRegAlloc &PRA ) const;
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};
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@ -596,8 +461,7 @@ class UltraSparcRegInfo : public MachineRegInfo
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class UltraSparcSchedInfo: public MachineSchedInfo {
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public:
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/*ctor*/ UltraSparcSchedInfo (const TargetMachine& tgt);
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/*dtor*/ virtual ~UltraSparcSchedInfo () {}
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UltraSparcSchedInfo(const TargetMachine &tgt);
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protected:
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virtual void initializeResources();
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};
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@ -614,7 +478,7 @@ protected:
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class UltraSparcFrameInfo: public MachineFrameInfo {
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public:
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/*ctor*/ UltraSparcFrameInfo(const TargetMachine& tgt) : MachineFrameInfo(tgt) {}
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UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
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public:
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int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
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@ -1,4 +1,4 @@
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#include "SparcInternals.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/IGNode.h"
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#include "llvm/Target/Sparc.h"
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#include <iostream>
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@ -17,8 +17,7 @@ using std::cerr;
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// If both above fail, spill.
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//
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//-----------------------------------------------------------------------------
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void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
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{
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void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const {
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LiveRange *LR = Node->getParentLR();
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unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
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@ -124,11 +123,6 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
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//
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if (!ColorFound)
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LR->markForSpill(); // no color found - must spill
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if( DEBUG_RA)
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UltraSparcRegInfo::printReg( LR );
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}
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@ -213,10 +207,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
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if( ColorFound >= 0 ) { // if we could find a color
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LR->setColor(ColorFound);
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if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
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return;
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}
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else {
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} else {
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// if we didn't find a color becuase the LR was single precision or
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// all f32-f63 range is filled, we try to allocate a register from
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@ -241,7 +233,6 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
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if( ColorFound >= 0 ) { // if we could find a color
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LR->setColor(ColorFound);
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if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
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return;
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}
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else if( isCallInterf ) {
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@ -260,18 +251,11 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
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if( ColorFound >= 0 ) {
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LR->setColor(ColorFound); // first color found in preffered order
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LR->markForSaveAcrossCalls();
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if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
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return;
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}
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} else {
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// we are here because no color could be found
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LR->markForSpill(); // no color found - must spill
|
||||
if( DEBUG_RA) UltraSparcRegInfo::printReg( LR );
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
@ -279,44 +263,24 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
|
||||
// Finds the first available color in the range [Start,End] depending on the
|
||||
// type of the Node (i.e., float/double)
|
||||
//-----------------------------------------------------------------------------
|
||||
int SparcFloatRegClass::findFloatColor(const LiveRange *const LR,
|
||||
unsigned Start,
|
||||
unsigned End,
|
||||
bool IsColorUsedArr[] ) const {
|
||||
|
||||
int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
|
||||
unsigned Start, unsigned End,
|
||||
bool IsColorUsedArr[] ) const {
|
||||
bool ColorFound = false;
|
||||
unsigned c;
|
||||
|
||||
if (LR->getTypeID() == Type::DoubleTyID) {
|
||||
|
||||
// find first unused color for a double
|
||||
for( c=Start; c < End ;c+= 2){
|
||||
for (c=Start; c < End ; c+= 2)
|
||||
if (!IsColorUsedArr[c] && !IsColorUsedArr[c+1])
|
||||
{ ColorFound=true; break; }
|
||||
}
|
||||
|
||||
return c;
|
||||
} else {
|
||||
|
||||
// find first unused color for a single
|
||||
for( c=Start; c < End; c++) {
|
||||
if( ! IsColorUsedArr[ c ] ) { ColorFound=true; break; }
|
||||
}
|
||||
for (c = Start; c < End; c++)
|
||||
if (!IsColorUsedArr[c])
|
||||
return c;
|
||||
}
|
||||
|
||||
if( ColorFound ) return c;
|
||||
else return -1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -17,34 +17,27 @@
|
||||
|
||||
// Int register names in same order as enum in class SparcIntRegOrder
|
||||
|
||||
static const std::string IntRegNames[] =
|
||||
{
|
||||
static const std::string IntRegNames[] = {
|
||||
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
|
||||
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
|
||||
"i0", "i1", "i2", "i3", "i4", "i5",
|
||||
"i6", "i7",
|
||||
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
|
||||
"o6" };
|
||||
"o6"
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcIntRegOrder{
|
||||
|
||||
public:
|
||||
|
||||
enum RegsInPrefOrder // colors possible for a LR (in preferred order)
|
||||
{
|
||||
struct SparcIntRegOrder {
|
||||
enum RegsInPrefOrder { // colors possible for a LR (in preferred order)
|
||||
// --- following colors are volatile across function calls
|
||||
// %g0 can't be used for coloring - always 0
|
||||
|
||||
|
||||
o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
|
||||
|
||||
// %o6 is sp,
|
||||
// all %0's can get modified by a call
|
||||
|
||||
// --- following colors are NON-volatile across function calls
|
||||
|
||||
l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
|
||||
i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
|
||||
|
||||
@ -64,7 +57,6 @@ class SparcIntRegOrder{
|
||||
// enumeration of %o0 (change StartOfAllRegs below)
|
||||
// change isRegVloatile method below
|
||||
// Also change IntRegNames above.
|
||||
|
||||
};
|
||||
|
||||
// max # of colors reg coloring can allocate
|
||||
@ -75,41 +67,26 @@ class SparcIntRegOrder{
|
||||
static unsigned int const NumOfAllRegs = o6 + 1;
|
||||
|
||||
|
||||
static const std::string getRegName(const unsigned reg) {
|
||||
static const std::string getRegName(unsigned reg) {
|
||||
assert( reg < NumOfAllRegs );
|
||||
return IntRegNames[reg];
|
||||
}
|
||||
|
||||
static unsigned int getRegNumInCallersWindow(const unsigned reg) {
|
||||
if (reg <= l7 || reg == o6) {
|
||||
assert(0 && "registers o0-o7 and l0-l7 are not visible in caller");
|
||||
return reg;
|
||||
}
|
||||
if (reg <= i7)
|
||||
return reg - (i0 - o0);
|
||||
assert((reg >= g0 || reg <= g7) && "Unrecognized integer register number");
|
||||
return reg;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcIntRegClass : public MachineRegClassInfo
|
||||
{
|
||||
public:
|
||||
|
||||
struct SparcIntRegClass : public MachineRegClassInfo {
|
||||
SparcIntRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID,
|
||||
SparcIntRegOrder::NumOfAvailRegs,
|
||||
SparcIntRegOrder::NumOfAllRegs)
|
||||
{ }
|
||||
SparcIntRegOrder::NumOfAllRegs) { }
|
||||
|
||||
void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const;
|
||||
|
||||
inline bool isRegVolatile(const int Reg) const {
|
||||
inline bool isRegVolatile(int Reg) const {
|
||||
return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -157,37 +134,27 @@ class SparcFloatRegOrder{
|
||||
static unsigned int const StartOfAllRegs = f0;
|
||||
|
||||
|
||||
static const std::string getRegName(const unsigned reg) {
|
||||
static const std::string getRegName(unsigned reg) {
|
||||
assert (reg < NumOfAllRegs);
|
||||
return FloatRegNames[reg];
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcFloatRegClass : public MachineRegClassInfo
|
||||
{
|
||||
private:
|
||||
|
||||
int findFloatColor(const LiveRange *const LR, unsigned Start,
|
||||
class SparcFloatRegClass : public MachineRegClassInfo {
|
||||
int findFloatColor(const LiveRange *LR, unsigned Start,
|
||||
unsigned End, bool IsColorUsedArr[]) const;
|
||||
|
||||
public:
|
||||
|
||||
SparcFloatRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID,
|
||||
SparcFloatRegOrder::NumOfAvailRegs,
|
||||
SparcFloatRegOrder::NumOfAllRegs)
|
||||
{ }
|
||||
SparcFloatRegOrder::NumOfAllRegs) {}
|
||||
|
||||
void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const;
|
||||
|
||||
// according to Sparc 64 ABI, all %fp regs are volatile
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
|
||||
inline bool isRegVolatile(int Reg) const { return true; }
|
||||
};
|
||||
|
||||
|
||||
@ -203,34 +170,25 @@ class SparcFloatRegClass : public MachineRegClassInfo
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
static const std::string IntCCRegNames[] =
|
||||
{
|
||||
static const std::string IntCCRegNames[] = {
|
||||
"xcc", "ccr"
|
||||
};
|
||||
|
||||
|
||||
class SparcIntCCRegOrder{
|
||||
|
||||
public:
|
||||
|
||||
struct SparcIntCCRegOrder {
|
||||
enum RegsInPrefOrder {
|
||||
|
||||
xcc, ccr // only one is available - see the note above
|
||||
};
|
||||
|
||||
static const std::string getRegName(const unsigned reg) {
|
||||
static const std::string getRegName(unsigned reg) {
|
||||
assert(reg < 2);
|
||||
return IntCCRegNames[reg];
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcIntCCRegClass : public MachineRegClassInfo
|
||||
{
|
||||
public:
|
||||
|
||||
struct SparcIntCCRegClass : public MachineRegClassInfo {
|
||||
SparcIntCCRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID, 1, 2) { }
|
||||
|
||||
@ -240,7 +198,7 @@ public:
|
||||
|
||||
// according to Sparc 64 ABI, %ccr is volatile
|
||||
//
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
inline bool isRegVolatile(int Reg) const { return true; }
|
||||
|
||||
};
|
||||
|
||||
@ -252,35 +210,22 @@ public:
|
||||
// Only 4 Float CC registers are available
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
static const std::string FloatCCRegNames[] =
|
||||
{
|
||||
static const std::string FloatCCRegNames[] = {
|
||||
"fcc0", "fcc1", "fcc2", "fcc3"
|
||||
};
|
||||
|
||||
|
||||
class SparcFloatCCRegOrder{
|
||||
|
||||
public:
|
||||
|
||||
struct SparcFloatCCRegOrder{
|
||||
enum RegsInPrefOrder {
|
||||
|
||||
fcc0, fcc1, fcc2, fcc3
|
||||
};
|
||||
|
||||
static const std::string getRegName(const unsigned reg) {
|
||||
static const std::string getRegName(unsigned reg) {
|
||||
assert (reg < 4);
|
||||
return FloatCCRegNames[reg];
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
class SparcFloatCCRegClass : public MachineRegClassInfo
|
||||
{
|
||||
public:
|
||||
|
||||
struct SparcFloatCCRegClass : public MachineRegClassInfo {
|
||||
SparcFloatCCRegClass(unsigned ID)
|
||||
: MachineRegClassInfo(ID, 4, 4) { }
|
||||
|
||||
@ -291,15 +236,9 @@ public:
|
||||
Node->setColor(c);
|
||||
}
|
||||
|
||||
|
||||
// according to Sparc 64 ABI, all %fp CC regs are volatile
|
||||
//
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
|
||||
inline bool isRegVolatile(int Reg) const { return true; }
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -5,18 +5,83 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/Target/Sparc.h"
|
||||
#include "SparcInternals.h"
|
||||
#include "llvm/Method.h"
|
||||
#include "llvm/iTerminators.h"
|
||||
#include "llvm/iOther.h"
|
||||
#include "llvm/CodeGen/InstrSelection.h"
|
||||
#include "SparcRegClassInfo.h"
|
||||
#include "llvm/Target/Sparc.h"
|
||||
#include "llvm/CodeGen/MachineCodeForMethod.h"
|
||||
#include "llvm/CodeGen/PhyRegAlloc.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/Analysis/LiveVar/LiveVarSet.h"
|
||||
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
|
||||
#include "llvm/iTerminators.h"
|
||||
#include "llvm/iOther.h"
|
||||
#include "llvm/DerivedTypes.h"
|
||||
#include <iostream>
|
||||
using std::cerr;
|
||||
|
||||
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
|
||||
: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
|
||||
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
|
||||
|
||||
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
|
||||
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
|
||||
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
|
||||
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
|
||||
|
||||
assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
|
||||
"32 Float regs are used for float arg passing");
|
||||
}
|
||||
|
||||
|
||||
// getZeroRegNum - returns the register that contains always zero this is the
|
||||
// unified register number
|
||||
//
|
||||
int UltraSparcRegInfo::getZeroRegNum() const { return SparcIntRegOrder::g0; }
|
||||
|
||||
// getCallAddressReg - returns the reg used for pushing the address when a
|
||||
// method is called. This can be used for other purposes between calls
|
||||
//
|
||||
unsigned UltraSparcRegInfo::getCallAddressReg() const {
|
||||
return SparcIntRegOrder::o7;
|
||||
}
|
||||
|
||||
// Returns the register containing the return address.
|
||||
// It should be made sure that this register contains the return
|
||||
// value when a return instruction is reached.
|
||||
//
|
||||
unsigned UltraSparcRegInfo::getReturnAddressReg() const {
|
||||
return SparcIntRegOrder::i7;
|
||||
}
|
||||
|
||||
// given the unified register number, this gives the name
|
||||
// for generating assembly code or debugging.
|
||||
//
|
||||
const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
|
||||
if( reg < 32 )
|
||||
return SparcIntRegOrder::getRegName(reg);
|
||||
else if ( reg < (64 + 32) )
|
||||
return SparcFloatRegOrder::getRegName( reg - 32);
|
||||
else if( reg < (64+32+4) )
|
||||
return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
|
||||
else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
|
||||
return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
|
||||
else if (reg== InvalidRegNum) //****** TODO: Remove */
|
||||
return "<*NoReg*>";
|
||||
else
|
||||
assert(0 && "Invalid register number");
|
||||
return "";
|
||||
}
|
||||
|
||||
unsigned UltraSparcRegInfo::getFramePointer() const {
|
||||
return SparcIntRegOrder::i6;
|
||||
}
|
||||
|
||||
unsigned UltraSparcRegInfo::getStackPointer() const {
|
||||
return SparcIntRegOrder::o6;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Finds the return value of a sparc specific call instruction
|
||||
//---------------------------------------------------------------------------
|
||||
@ -41,8 +106,7 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
|
||||
if(NumOfImpRefs > 0)
|
||||
if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
|
||||
return CallMI->getImplicitRef(NumOfImpRefs-1);
|
||||
}
|
||||
else
|
||||
} else
|
||||
assert(0 && "OpCode must be CALL/JMPL for a call instr");
|
||||
|
||||
return NULL;
|
||||
@ -55,11 +119,9 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
|
||||
//---------------------------------------------------------------------------
|
||||
const Value *
|
||||
UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI) const {
|
||||
|
||||
unsigned OpCode = CallMI->getOpCode();
|
||||
|
||||
if (OpCode == CALL) {
|
||||
|
||||
unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
|
||||
|
||||
assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
|
||||
@ -68,67 +130,110 @@ UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI)const {
|
||||
//
|
||||
return CallMI->getImplicitRef(NumOfImpRefs-1);
|
||||
|
||||
}
|
||||
else if( OpCode == JMPLCALL ) {
|
||||
|
||||
} else if(OpCode == JMPLCALL) {
|
||||
MachineOperand &MO = (MachineOperand &)CallMI->getOperand(2);
|
||||
return MO.getVRegValue();
|
||||
|
||||
}
|
||||
else
|
||||
|
||||
assert(0 && "OpCode must be CALL/JMPL for a call instr");
|
||||
|
||||
assert(0 && "There must be a return addr for a call instr");
|
||||
|
||||
return NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
// The following 3 methods are used to find the RegType (see enum above)
|
||||
// of a LiveRange, Value and using the unified RegClassID
|
||||
//
|
||||
int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
|
||||
unsigned Typ;
|
||||
switch (LR->getRegClass()->getID()) {
|
||||
case IntRegClassID: return IntRegType;
|
||||
case FloatRegClassID:
|
||||
Typ = LR->getTypeID();
|
||||
if (Typ == Type::FloatTyID)
|
||||
return FPSingleRegType;
|
||||
else if (Typ == Type::DoubleTyID)
|
||||
return FPDoubleRegType;
|
||||
assert(0 && "Unknown type in FloatRegClass");
|
||||
|
||||
case IntCCRegClassID: return IntCCRegType;
|
||||
case FloatCCRegClassID: return FloatCCRegType;
|
||||
default: assert( 0 && "Unknown reg class ID");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int UltraSparcRegInfo::getRegType(const Value *Val) const {
|
||||
unsigned Typ;
|
||||
|
||||
switch (getRegClassIDOfValue(Val)) {
|
||||
case IntRegClassID: return IntRegType;
|
||||
case FloatRegClassID:
|
||||
Typ = Val->getType()->getPrimitiveID();
|
||||
if (Typ == Type::FloatTyID)
|
||||
return FPSingleRegType;
|
||||
else if (Typ == Type::DoubleTyID)
|
||||
return FPDoubleRegType;
|
||||
assert(0 && "Unknown type in FloatRegClass");
|
||||
|
||||
case IntCCRegClassID: return IntCCRegType;
|
||||
case FloatCCRegClassID: return FloatCCRegType ;
|
||||
default: assert(0 && "Unknown reg class ID");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int UltraSparcRegInfo::getRegType(int reg) const {
|
||||
if (reg < 32)
|
||||
return IntRegType;
|
||||
else if (reg < (32 + 32))
|
||||
return FPSingleRegType;
|
||||
else if (reg < (64 + 32))
|
||||
return FPDoubleRegType;
|
||||
else if (reg < (64+32+4))
|
||||
return FloatCCRegType;
|
||||
else if (reg < (64+32+4+2))
|
||||
return IntCCRegType;
|
||||
else
|
||||
assert(0 && "Invalid register number in getRegType");
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Finds the # of actual arguments of the call instruction
|
||||
//---------------------------------------------------------------------------
|
||||
const unsigned
|
||||
unsigned
|
||||
UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
|
||||
|
||||
unsigned OpCode = CallMI->getOpCode();
|
||||
unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
|
||||
int NumArgs = -1;
|
||||
|
||||
if (OpCode == CALL) {
|
||||
|
||||
switch (NumOfImpRefs) {
|
||||
|
||||
case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
|
||||
|
||||
case 1: NumArgs = 0;
|
||||
break;
|
||||
|
||||
case 1: return 0;
|
||||
default: // two or more implicit refs
|
||||
if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
|
||||
NumArgs = NumOfImpRefs - 2; // i.e., NumOfImpRef-2 is the ret val
|
||||
return NumOfImpRefs - 2;
|
||||
else
|
||||
NumArgs = NumOfImpRefs - 1;
|
||||
return NumOfImpRefs - 1;
|
||||
}
|
||||
|
||||
}
|
||||
else if( OpCode == JMPLCALL ) {
|
||||
} else if (OpCode == JMPLCALL) {
|
||||
|
||||
// The last implicit operand is the return value of a JMPL instr
|
||||
if( NumOfImpRefs > 0 ) {
|
||||
if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
|
||||
NumArgs = NumOfImpRefs - 1; // i.e., NumOfImpRef-1 is the ret val
|
||||
return NumOfImpRefs - 1;
|
||||
else
|
||||
NumArgs = NumOfImpRefs;
|
||||
return NumOfImpRefs;
|
||||
}
|
||||
else
|
||||
NumArgs = NumOfImpRefs;
|
||||
return NumOfImpRefs;
|
||||
}
|
||||
else
|
||||
assert(0 && "OpCode must be CALL/JMPL for a call instr");
|
||||
|
||||
assert( (NumArgs != -1) && "Internal error in getCallInstNumArgs" );
|
||||
return (unsigned) NumArgs;
|
||||
assert(0 && "OpCode must be CALL/JMPL for a call instr");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -215,7 +320,7 @@ void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
|
||||
// If the arg is passed on stack due to the lack of regs, NOTHING will be
|
||||
// done - it will be colored (or spilled) as a normal live range.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
|
||||
void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *Meth,
|
||||
LiveRangeInfo& LRI) const
|
||||
{
|
||||
|
||||
@ -264,9 +369,9 @@ void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
|
||||
// the correct hardware registers if they did not receive the correct
|
||||
// (suggested) color through graph coloring.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
|
||||
void UltraSparcRegInfo::colorMethodArgs(const Method *Meth,
|
||||
LiveRangeInfo &LRI,
|
||||
AddedInstrns *const FirstAI) const {
|
||||
AddedInstrns *FirstAI) const {
|
||||
|
||||
// get the argument list
|
||||
const Method::ArgumentListType& ArgList = Meth->getArgumentList();
|
||||
@ -394,12 +499,11 @@ void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
|
||||
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// This method is called before graph coloring to suggest colors to the
|
||||
// outgoing call args and the return value of the call.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
|
||||
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
|
||||
LiveRangeInfo& LRI,
|
||||
std::vector<RegClass *> RCList) const {
|
||||
|
||||
@ -423,13 +527,10 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
|
||||
|
||||
|
||||
if (RetVal) {
|
||||
|
||||
assert ((!LRI.getLiveRangeForValue(RetVal)) &&
|
||||
"LR for ret Value of call already definded!");
|
||||
|
||||
|
||||
// create a new LR for the return value
|
||||
|
||||
LiveRange *RetValLR = new LiveRange();
|
||||
RetValLR->add(RetVal);
|
||||
unsigned RegClassID = getRegClassIDOfValue(RetVal);
|
||||
@ -443,7 +544,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
|
||||
else if (RegClassID == FloatRegClassID )
|
||||
RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
|
||||
else assert( 0 && "Unknown reg class for return value of call\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -469,7 +569,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
|
||||
printValue(CallArg); cerr << "\n";
|
||||
}
|
||||
assert(0 && "NO LR for call arg");
|
||||
// continue;
|
||||
}
|
||||
|
||||
unsigned RegType = getRegType( LR );
|
||||
@ -504,9 +603,9 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
|
||||
// to instert copy instructions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
|
||||
LiveRangeInfo &LRI,
|
||||
AddedInstrns *const CallAI,
|
||||
AddedInstrns *CallAI,
|
||||
PhyRegAlloc &PRA,
|
||||
const BasicBlock *BB) const {
|
||||
|
||||
@ -667,8 +766,6 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
|
||||
|
||||
if (LR->hasColor()) {
|
||||
|
||||
|
||||
unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
|
||||
|
||||
// if LR received the correct color, nothing to do
|
||||
@ -707,9 +804,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
AddedInstrnsBefore.push_back( AdMI );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
else {
|
||||
} else {
|
||||
// Now, we have to pass the arg on stack. Since LR received a register
|
||||
// we just have to move that register to the stack position where
|
||||
// the argument must be passed
|
||||
@ -727,9 +822,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
else { // LR is not colored (i.e., spilled)
|
||||
} else { // LR is not colored (i.e., spilled)
|
||||
|
||||
if( isArgInReg ) {
|
||||
|
||||
@ -792,9 +885,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
|
||||
cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
} // for each parameter in call instruction
|
||||
|
||||
|
||||
@ -815,7 +906,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
if (DEBUG_RA) {
|
||||
cerr << "\nAfter reordering instrns: \n";
|
||||
for(unsigned i = 0; i < TmpVec.size(); i++)
|
||||
cerr << *(TmpVec[i]);
|
||||
cerr << *TmpVec[i];
|
||||
}
|
||||
|
||||
// copy the results back from TmpVec to InstrnsBefore
|
||||
@ -828,18 +919,15 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
//
|
||||
insertCallerSavingCode(CallMI, BB, PRA);
|
||||
|
||||
|
||||
// Reset optional args area again to be safe
|
||||
PRA.mcInfo.resetOptionalArgs(target);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// This method is called for an LLVM return instruction to identify which
|
||||
// values will be returned from this method and to suggest colors.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
|
||||
void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
|
||||
LiveRangeInfo &LRI) const {
|
||||
|
||||
assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
|
||||
@ -866,12 +954,9 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
|
||||
|
||||
if (RegClassID == IntRegClassID)
|
||||
LR->setSuggestedColor(SparcIntRegOrder::i0);
|
||||
|
||||
else if (RegClassID == FloatRegClassID)
|
||||
LR->setSuggestedColor(SparcFloatRegOrder::f0);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -882,9 +967,9 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
|
||||
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
|
||||
// have to put a load instruction.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
|
||||
void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
|
||||
LiveRangeInfo &LRI,
|
||||
AddedInstrns *const RetAI) const {
|
||||
AddedInstrns *RetAI) const {
|
||||
|
||||
assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
|
||||
|
||||
@ -894,7 +979,7 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
|
||||
// The first implicit operand is the return value of a return instr
|
||||
const Value *RetVal = RetMI->getImplicitRef(0);
|
||||
|
||||
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
|
||||
LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
|
||||
|
||||
if( ! LR ) {
|
||||
cerr << "\nNo LR for:";
|
||||
@ -919,8 +1004,7 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
|
||||
|
||||
// if the LR received the correct color, NOTHING to do
|
||||
|
||||
if( LR->hasColor() )
|
||||
if( LR->getColor() == CorrectCol )
|
||||
if (LR->hasColor() && LR->getColor() == CorrectCol)
|
||||
return;
|
||||
|
||||
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
||||
@ -956,9 +1040,8 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
|
||||
// register number
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
|
||||
const unsigned DestReg,
|
||||
const int RegType) const {
|
||||
MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
|
||||
int RegType) const {
|
||||
|
||||
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
|
||||
"Invalid Register");
|
||||
@ -1002,16 +1085,11 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
|
||||
const unsigned DestPtrReg,
|
||||
const int Offset,
|
||||
const int RegType) const {
|
||||
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
|
||||
unsigned DestPtrReg,
|
||||
int Offset, int RegType) const {
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch( RegType ) {
|
||||
|
||||
case IntRegType:
|
||||
case FloatCCRegType:
|
||||
MI = new MachineInstr(STX, 3);
|
||||
@ -1054,15 +1132,12 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
|
||||
const int Offset,
|
||||
const unsigned DestReg,
|
||||
const int RegType) const {
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
|
||||
int Offset,
|
||||
unsigned DestReg,
|
||||
int RegType) const {
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch (RegType) {
|
||||
|
||||
case IntRegType:
|
||||
case FloatCCRegType:
|
||||
MI = new MachineInstr(LDX, 3);
|
||||
@ -1110,7 +1185,6 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
|
||||
|
||||
|
||||
MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
|
||||
|
||||
int RegType = getRegType( Src );
|
||||
|
||||
assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
|
||||
@ -1118,9 +1192,7 @@ MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch( RegType ) {
|
||||
|
||||
case IntRegType:
|
||||
|
||||
MI = new MachineInstr(ADD, 3);
|
||||
MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
|
||||
MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
|
||||
@ -1186,7 +1258,6 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
|
||||
const Value *RetVal = getCallInstRetVal( MInst );
|
||||
|
||||
if (RetVal) {
|
||||
|
||||
LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
|
||||
assert(RetValLR && "No LR for RetValue of call");
|
||||
|
||||
@ -1198,7 +1269,6 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
|
||||
|
||||
|
||||
const LiveVarSet *LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
|
||||
|
||||
LiveVarSet::const_iterator LIt = LVSetAft->begin();
|
||||
|
||||
// for each live var in live variable set after machine inst
|
||||
@ -1345,13 +1415,10 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
|
||||
// number.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
MI = new MachineInstr(RDCCR, 2);
|
||||
MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
|
||||
MachineInstr * MI = new MachineInstr(RDCCR, 2);
|
||||
MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
|
||||
MI->SetMachineOperand(1, IntReg, true);
|
||||
|
||||
return MI;
|
||||
}
|
||||
|
||||
@ -1360,14 +1427,11 @@ MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
|
||||
// number.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
MI = new MachineInstr(WRCCR, 3);
|
||||
MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
|
||||
MachineInstr *MI = new MachineInstr(WRCCR, 3);
|
||||
MI->SetMachineOperand(0, IntReg, false);
|
||||
MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
|
||||
MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
|
||||
|
||||
return MI;
|
||||
}
|
||||
|
||||
@ -1378,10 +1442,8 @@ MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
|
||||
// Print the register assigned to a LR
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
|
||||
|
||||
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
|
||||
unsigned RegClassID = (LR->getRegClass())->getID();
|
||||
|
||||
cerr << " *Node " << (LR->getUserIGNode())->getIndex();
|
||||
|
||||
if (!LR->hasColor()) {
|
||||
@ -1457,14 +1519,11 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
|
||||
|
||||
*/
|
||||
|
||||
|
||||
bool CouldMoveAll;
|
||||
bool DebugPrint = false;
|
||||
|
||||
do {
|
||||
|
||||
CouldMoveAll = true;
|
||||
|
||||
std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
|
||||
|
||||
for( ; DefIt != UnordVec.end(); ++DefIt ) {
|
||||
@ -1496,8 +1555,6 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
|
||||
if( UseInst == NULL) continue;
|
||||
|
||||
// for each inst (UseInst) that is below the DefInst do ...
|
||||
|
||||
|
||||
MachineOperand& UseOp = UseInst->getOperand(0);
|
||||
|
||||
if( ! UseOp.opIsDef() &&
|
||||
@ -1545,26 +1602,20 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
|
||||
|
||||
} while(!CouldMoveAll);
|
||||
|
||||
|
||||
if (DebugPrint) {
|
||||
cerr << "\nAdded instructions were reordered to:\n";
|
||||
for(unsigned int i=0; i < OrdVec.size(); i++)
|
||||
cerr << *(OrdVec[i]);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
|
||||
MachineInstr *UnordInst,
|
||||
PhyRegAlloc &PRA) const {
|
||||
|
||||
MachineOperand& UseOp = UnordInst->getOperand(0);
|
||||
|
||||
if( ! UseOp.opIsDef() &&
|
||||
@ -1650,11 +1701,4 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
|
||||
}
|
||||
|
||||
}// if the operand in UnordInst is a use
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user