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Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense.
llvm-svn: 200824
This commit is contained in:
Craig Topper
parent
2e0202b75e
commit
4c6c325efa
@ -14034,9 +14034,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::OR: return "X86ISD::OR";
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case X86ISD::XOR: return "X86ISD::XOR";
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case X86ISD::AND: return "X86ISD::AND";
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case X86ISD::BLSI: return "X86ISD::BLSI";
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case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
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case X86ISD::BLSR: return "X86ISD::BLSR";
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case X86ISD::BZHI: return "X86ISD::BZHI";
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case X86ISD::BEXTR: return "X86ISD::BEXTR";
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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@ -18089,9 +18086,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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if (R.getNode())
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return R;
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// Create BLSI, BLSR, and BZHI instructions
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// BLSI is X & (-X)
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// BLSR is X & (X-1)
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// Create BEXTR and BZHI instructions
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// BZHI is X & ((1 << Y) - 1)
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// BEXTR is ((X >> imm) & (2**size-1))
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if (VT == MVT::i32 || VT == MVT::i64) {
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@ -18099,28 +18094,6 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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SDValue N1 = N->getOperand(1);
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SDLoc DL(N);
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if (Subtarget->hasBMI()) {
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// Check LHS for neg
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if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
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isZero(N0.getOperand(0)))
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return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
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// Check RHS for neg
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if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
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isZero(N1.getOperand(0)))
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return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
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// Check LHS for X-1
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if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
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isAllOnes(N0.getOperand(1)))
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return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
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// Check RHS for X-1
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if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
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isAllOnes(N1.getOperand(1)))
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return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
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}
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if (Subtarget->hasBMI2()) {
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// Check for (and (add (shl 1, Y), -1), X)
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if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
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@ -18396,7 +18369,6 @@ static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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@ -18406,28 +18378,6 @@ static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
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return RV;
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}
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// Try forming BMI if it is available.
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if (!Subtarget->hasBMI())
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return SDValue();
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if (VT != MVT::i32 && VT != MVT::i64)
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return SDValue();
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assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
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// Create BLSMSK instructions by finding X ^ (X-1)
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDLoc DL(N);
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if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
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isAllOnes(N0.getOperand(1)))
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return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
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if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
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isAllOnes(N1.getOperand(1)))
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return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
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return SDValue();
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}
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@ -295,9 +295,6 @@ namespace llvm {
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ADD, SUB, ADC, SBB, SMUL,
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INC, DEC, OR, XOR, AND,
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BLSI, // BLSI - Extract lowest set isolated bit
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BLSMSK, // BLSMSK - Get mask up to lowest set bit
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BLSR, // BLSR - Reset lowest set bit
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BZHI, // BZHI - Zero high bits
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BEXTR, // BEXTR - Bit field extract
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@ -249,9 +249,6 @@ def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
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def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
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[SDNPCommutative]>;
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def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
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def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
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def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
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def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
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def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
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@ -1978,30 +1975,47 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
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}
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multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
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RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
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PatFrag ld_frag> {
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RegisterClass RC, X86MemOperand x86memop> {
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let hasSideEffects = 0 in {
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def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
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[]>, T8, VEX_4V;
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let mayLoad = 1 in
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def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
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T8, VEX_4V;
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[]>, T8, VEX_4V;
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}
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}
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
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X86blsr, loadi32>;
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defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
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X86blsr, loadi64>, VEX_W;
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defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
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X86blsmsk, loadi32>;
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defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
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X86blsmsk, loadi64>, VEX_W;
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defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
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X86blsi, loadi32>;
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defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
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X86blsi, loadi64>, VEX_W;
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defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
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defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
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defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
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defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
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defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
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defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
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}
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//===----------------------------------------------------------------------===//
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// Pattern fragments to auto generate BMI instructions.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasBMI] in {
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// FIXME: patterns for the load versions are not implemented
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def : Pat<(and GR32:$src, (add GR32:$src, -1)),
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(BLSR32rr GR32:$src)>;
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def : Pat<(and GR64:$src, (add GR64:$src, -1)),
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(BLSR64rr GR64:$src)>;
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def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
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(BLSMSK32rr GR32:$src)>;
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def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
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(BLSMSK64rr GR64:$src)>;
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def : Pat<(and GR32:$src, (ineg GR32:$src)),
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(BLSI32rr GR32:$src)>;
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def : Pat<(and GR64:$src, (ineg GR64:$src)),
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(BLSI64rr GR64:$src)>;
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}
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multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
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