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On x86, f32 / f64 nodes share the same registers as 128-bit vector values.
llvm-svn: 109450
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@ -1190,6 +1190,32 @@ unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
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return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
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}
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std::pair<const TargetRegisterClass*, uint8_t>
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X86TargetLowering::findRepresentativeClass(EVT VT) const{
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const TargetRegisterClass *RRC = 0;
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uint8_t Cost = 1;
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switch (VT.getSimpleVT().SimpleTy) {
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default:
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return TargetLowering::findRepresentativeClass(VT);
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case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
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RRC = (Subtarget->is64Bit()
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? X86::GR64RegisterClass : X86::GR32RegisterClass);
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break;
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case MVT::v8i8: case MVT::v4i16:
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case MVT::v2i32: case MVT::v1i64:
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RRC = X86::VR64RegisterClass;
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break;
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case MVT::f32: case MVT::f64:
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case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
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case MVT::v4f32: case MVT::v2f64:
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case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
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case MVT::v4f64:
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RRC = X86::VR128RegisterClass;
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break;
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}
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return std::make_pair(RRC, Cost);
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}
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unsigned
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X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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@ -599,6 +599,10 @@ namespace llvm {
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/// appropriate.
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virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
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protected:
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(EVT VT) const;
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private:
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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