RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-21 03:05:15 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[SLP] Test for trunc vectorization, NFC.

Browse Source 
llvm-svn: 323556
This commit is contained in:
Alexey Bataev 2018-01-26 20:07:55 +00:00
parent 292f7a9faf
commit 4d3a387405
1 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
test/Transforms/SLPVectorizer/X86/sign-extend.ll
View File

@ -30,3 +30,36 @@ entry:
%vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
ret <4 x i32> %vecinit9
}
define <4 x i16> @truncate_v_v(<4 x i32> %lhs) {
; CHECK-LABEL: @truncate_v_v(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i32> [[LHS:%.*]], i32 0
; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[VECEXT]] to i16
; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i16> undef, i16 [[CONV]], i32 0
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <4 x i32> [[LHS]], i32 1
; CHECK-NEXT: [[CONV2:%.*]] = trunc i32 [[VECEXT1]] to i16
; CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x i16> [[VECINIT]], i16 [[CONV2]], i32 1
; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <4 x i32> [[LHS]], i32 2
; CHECK-NEXT: [[CONV5:%.*]] = trunc i32 [[VECEXT4]] to i16
; CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <4 x i16> [[VECINIT3]], i16 [[CONV5]], i32 2
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x i32> [[LHS]], i32 3
; CHECK-NEXT: [[CONV8:%.*]] = trunc i32 [[VECEXT7]] to i16
; CHECK-NEXT: [[VECINIT9:%.*]] = insertelement <4 x i16> [[VECINIT6]], i16 [[CONV8]], i32 3
; CHECK-NEXT: ret <4 x i16> [[VECINIT9]]
;
entry:
%vecext = extractelement <4 x i32> %lhs, i32 0
%conv = trunc i32 %vecext to i16
%vecinit = insertelement <4 x i16> undef, i16 %conv, i32 0
%vecext1 = extractelement <4 x i32> %lhs, i32 1
%conv2 = trunc i32 %vecext1 to i16
%vecinit3 = insertelement <4 x i16> %vecinit, i16 %conv2, i32 1
%vecext4 = extractelement <4 x i32> %lhs, i32 2
%conv5 = trunc i32 %vecext4 to i16
%vecinit6 = insertelement <4 x i16> %vecinit3, i16 %conv5, i32 2
%vecext7 = extractelement <4 x i32> %lhs, i32 3
%conv8 = trunc i32 %vecext7 to i16
%vecinit9 = insertelement <4 x i16> %vecinit6, i16 %conv8, i32 3
ret <4 x i16> %vecinit9
}