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[TargetLowering] Fix propagation of undefs in zero extension ops (PR40091)
As described on PR40091, we have several places where zext (and zext_vector_inreg) fold an undef input into an undef output. For zero extensions this is incorrect as the output should guarantee to least have the new upper bits set to zero. SimplifyDemandedVectorElts is the worst offender (and its the most likely to cause new undefs to appear) but DAGCombiner's tryToFoldExtendOfConstant has a similar issue. Thanks to @dmgreen for catching this. Differential Revision: https://reviews.llvm.org/D55883 llvm-svn: 349625
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@ -8064,10 +8064,15 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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unsigned NumElts = VT.getVectorNumElements();
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SDLoc DL(N);
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for (unsigned i=0; i != NumElts; ++i) {
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SDValue Op = N0->getOperand(i);
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if (Op->isUndef()) {
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Elts.push_back(DAG.getUNDEF(SVT));
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// For zero-extensions, UNDEF elements still guarantee to have the upper
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// bits set to zero.
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bool IsZext =
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Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG;
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for (unsigned i = 0; i != NumElts; ++i) {
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SDValue Op = N0.getOperand(i);
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if (Op.isUndef()) {
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Elts.push_back(IsZext ? DAG.getConstant(0, DL, SVT) : DAG.getUNDEF(SVT));
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continue;
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}
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@ -1848,6 +1848,13 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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return true;
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KnownZero = SrcZero.zextOrTrunc(NumElts);
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KnownUndef = SrcUndef.zextOrTrunc(NumElts);
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if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
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// zext(undef) upper bits are guaranteed to be zero.
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if (DemandedElts.isSubsetOf(KnownUndef))
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return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
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KnownUndef.clearAllBits();
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}
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break;
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}
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case ISD::OR:
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@ -1892,6 +1899,13 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
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KnownZero, TLO, Depth + 1))
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return true;
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if (Op.getOpcode() == ISD::ZERO_EXTEND) {
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// zext(undef) upper bits are guaranteed to be zero.
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if (DemandedElts.isSubsetOf(KnownUndef))
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return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
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KnownUndef.clearAllBits();
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}
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break;
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default: {
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
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@ -4,7 +4,7 @@
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define i64 @test(i64 %aa) {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
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; CHECK-NEXT: movi v0.8b, #137
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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@ -261,12 +261,12 @@ define <4 x i64> @test_zext_4i8_4i64() {
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define <4 x i16> @test_zext_4i8_4i16_undef() {
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; X32-LABEL: test_zext_4i8_4i16_undef:
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; X32: # %bb.0:
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253>
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,0,253]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_zext_4i8_4i16_undef:
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; X64: # %bb.0:
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253>
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,0,253]
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; X64-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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@ -279,12 +279,12 @@ define <4 x i16> @test_zext_4i8_4i16_undef() {
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define <4 x i32> @test_zext_4i8_4i32_undef() {
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; X32-LABEL: test_zext_4i8_4i32_undef:
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; X32: # %bb.0:
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = <0,u,2,u>
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,2,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_zext_4i8_4i32_undef:
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; X64: # %bb.0:
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = <0,u,2,u>
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,2,0]
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; X64-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 0, i32 0
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%2 = insertelement <4 x i8> %1, i8 undef, i32 1
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@ -297,12 +297,12 @@ define <4 x i32> @test_zext_4i8_4i32_undef() {
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define <4 x i64> @test_zext_4i8_4i64_undef() {
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; X32-LABEL: test_zext_4i8_4i64_undef:
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; X32: # %bb.0:
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; X32-NEXT: vmovaps {{.*#+}} ymm0 = <u,u,255,0,2,0,u,u>
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; X32-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,255,0,2,0,0,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_zext_4i8_4i64_undef:
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; X64: # %bb.0:
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; X64-NEXT: vmovaps {{.*#+}} ymm0 = <u,255,2,u>
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; X64-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,2,0]
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; X64-NEXT: retq
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%1 = insertelement <4 x i8> undef, i8 undef, i32 0
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%2 = insertelement <4 x i8> %1, i8 -1, i32 1
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@ -359,12 +359,12 @@ define <8 x i32> @test_zext_8i8_8i32() {
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define <8 x i16> @test_zext_8i8_8i16_undef() {
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; X32-LABEL: test_zext_8i8_8i16_undef:
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; X32: # %bb.0:
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253,u,251,u,249>
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; X32-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,0,253,0,251,0,249]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_zext_8i8_8i16_undef:
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; X64: # %bb.0:
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253,u,251,u,249>
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; X64-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,0,253,0,251,0,249]
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; X64-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 undef, i32 0
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%2 = insertelement <8 x i8> %1, i8 -1, i32 1
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@ -381,12 +381,12 @@ define <8 x i16> @test_zext_8i8_8i16_undef() {
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define <8 x i32> @test_zext_8i8_8i32_undef() {
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; X32-LABEL: test_zext_8i8_8i32_undef:
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; X32: # %bb.0:
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; X32-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,253,4,u,6,u>
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; X32-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,2,253,4,0,6,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_zext_8i8_8i32_undef:
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; X64: # %bb.0:
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; X64-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,253,4,u,6,u>
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; X64-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,2,253,4,0,6,0]
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; X64-NEXT: retq
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%1 = insertelement <8 x i8> undef, i8 0, i32 0
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%2 = insertelement <8 x i8> %1, i8 undef, i32 1
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