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[ExecutionDepsFix] Improve clearance calculation for loops
Summary:
In revision rL278321, ExecutionDepsFix learned how to pick a better
register for undef register reads, e.g. for instructions such as
`vcvtsi2sdq`. While this revision improved performance on a good number
of our benchmarks, it unfortunately also caused significant regressions
(up to 3x) on others. This regression turned out to be caused by loops
such as:
PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
^ |
+----------------------------------+
In the previous version of the clearance calculation, we would visit
the blocks in order, remembering for each whether there were any
incoming backedges from blocks that we hadn't processed yet and if
so queuing up the block to be re-processed. However, for loop structures
such as the above, this is clearly insufficient, since the block B
does not have any unknown backedges, so we do not see the false
dependency from the previous interation's Def of xmm registers in B.
To fix this, we need to consider all blocks that are part of the loop
and reprocess them one the correct clearance values are known. As
an optimization, we also want to avoid reprocessing any later blocks
that are not part of the loop.
In summary, the iteration order is as follows:
Before: PH A B C D A'
Corrected (Naive): PH A B C D A' B' C' D'
Corrected (w/ optimization): PH A B C A' B' C' D
To facilitate this optimization we introduce two new counters for each
basic block. The first counts how many of it's predecssors have
completed primary processing. The second counts how many of its
predecessors have completed all processing (we will call such a block
*done*. Now, the criteria to reprocess a block is as follows:
- All Predecessors have completed primary processing
- For x the number of predecessors that have completed primary
processing *at the time of primary processing of this block*,
the number of predecessors that are done has reached x.
The intuition behind this criterion is as follows:
We need to perform primary processing on all predecessors in order to
find out any direct defs in those predecessors. When predecessors are
done, we also know that we have information about indirect defs (e.g.
in block B though that were inherited through B->C->A->B). However,
we can't wait for all predecessors to be done, since that would
cause cyclic dependencies. However, it is guaranteed that all those
predecessors that are prior to us in reverse postorder will be done
before us. Since we iterate of the basic blocks in reverse postorder,
the number x above, is precisely the count of the number of predecessors
prior to us in reverse postorder.
Reviewers: myatsina
Differential Revision: https://reviews.llvm.org/D28759
llvm-svn: 293571
This commit is contained in:
Keno Fischer
parent
c1ccdd6039
commit
4db92211d7
@ -142,8 +142,30 @@ class ExeDepsFix : public MachineFunctionPass {
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std::vector<SmallVector<int, 1>> AliasMap;
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const unsigned NumRegs;
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LiveReg *LiveRegs;
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typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
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LiveOutMap LiveOuts;
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struct MBBInfo {
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// Keeps clearance and domain information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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LiveReg *OutRegs;
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// Whether we have gotten to this block in primary processing yet.
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bool PrimaryCompleted;
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// The number of predecessors for which primary processing has completed
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unsigned IncomingProcessed;
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// The value of `IncomingProcessed` at the start of primary processing
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unsigned PrimaryIncoming;
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// The number of predecessors for which all processing steps are done.
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unsigned IncomingCompleted;
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MBBInfo()
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: OutRegs(nullptr), PrimaryCompleted(false), IncomingProcessed(0),
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PrimaryIncoming(0), IncomingCompleted(0) {}
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};
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typedef DenseMap<MachineBasicBlock *, MBBInfo> MBBInfoMap;
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MBBInfoMap MBBInfos;
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/// List of undefined register reads in this block in forward order.
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std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
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@ -154,11 +176,6 @@ class ExeDepsFix : public MachineFunctionPass {
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/// Current instruction number.
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/// The first instruction in each basic block is 0.
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int CurInstr;
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/// True when the current block has a predecessor that hasn't been visited
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/// yet.
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bool SeenUnknownBackEdge;
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public:
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ExeDepsFix(const TargetRegisterClass *rc)
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: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
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@ -180,7 +197,6 @@ public:
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private:
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iterator_range<SmallVectorImpl<int>::const_iterator>
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regIndices(unsigned Reg) const;
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// DomainValue allocation.
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DomainValue *alloc(int domain = -1);
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DomainValue *retain(DomainValue *DV) {
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@ -199,8 +215,11 @@ private:
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void enterBasicBlock(MachineBasicBlock*);
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void leaveBasicBlock(MachineBasicBlock*);
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void visitInstr(MachineInstr*);
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void processDefs(MachineInstr*, bool Kill);
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bool isBlockDone(MachineBasicBlock *);
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void processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass);
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void updateSuccessors(MachineBasicBlock *MBB, bool PrimaryPass);
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bool visitInstr(MachineInstr *);
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void processDefs(MachineInstr *, bool breakDependency, bool Kill);
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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void pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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@ -360,9 +379,6 @@ bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) {
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/// Set up LiveRegs by merging predecessor live-out values.
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void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
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// Detect back-edges from predecessors we haven't processed yet.
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SeenUnknownBackEdge = false;
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// Reset instruction counter in each basic block.
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CurInstr = 0;
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@ -397,18 +413,21 @@ void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
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pe = MBB->pred_end(); pi != pe; ++pi) {
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LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
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if (fi == LiveOuts.end()) {
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SeenUnknownBackEdge = true;
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auto fi = MBBInfos.find(*pi);
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assert(fi != MBBInfos.end() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveReg *Incoming = fi->second.OutRegs;
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming == nullptr) {
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continue;
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}
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assert(fi->second && "Can't have NULL entries");
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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// Use the most recent predecessor def for each register.
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LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
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LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, Incoming[rx].Def);
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DomainValue *pdv = resolve(fi->second[rx].Value);
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DomainValue *pdv = resolve(Incoming[rx].Value);
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if (!pdv)
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continue;
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if (!LiveRegs[rx].Value) {
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@ -432,35 +451,34 @@ void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
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force(rx, pdv->getFirstDomain());
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}
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}
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DEBUG(dbgs() << "BB#" << MBB->getNumber()
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<< (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
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DEBUG(
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dbgs() << "BB#" << MBB->getNumber()
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<< (!isBlockDone(MBB) ? ": incomplete\n" : ": all preds known\n"));
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}
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void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
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assert(LiveRegs && "Must enter basic block first.");
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// Save live registers at end of MBB - used by enterBasicBlock().
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// Also use LiveOuts as a visited set to detect back-edges.
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bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
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LiveReg *OldOutRegs = MBBInfos[MBB].OutRegs;
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBInfos[MBB].OutRegs = LiveRegs;
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if (First) {
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// LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
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// the end of this block instead of the beginning.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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LiveRegs[i].Def -= CurInstr;
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} else {
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// Insertion failed, this must be the second pass.
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// While processing the basic block, we kept `Def` relative to the start
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// of the basic block for convenience. However, future use of this information
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// only cares about the clearance from the end of the block, so adjust
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// everything to be relative to the end of the basic block.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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LiveRegs[i].Def -= CurInstr;
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if (OldOutRegs) {
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// This must be the second pass.
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// Release all the DomainValues instead of keeping them.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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release(LiveRegs[i].Value);
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delete[] LiveRegs;
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release(OldOutRegs[i].Value);
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delete[] OldOutRegs;
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}
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LiveRegs = nullptr;
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}
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void ExeDepsFix::visitInstr(MachineInstr *MI) {
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if (MI->isDebugValue())
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return;
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bool ExeDepsFix::visitInstr(MachineInstr *MI) {
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// Update instructions with explicit execution domains.
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std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI);
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if (DomP.first) {
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@ -470,9 +488,7 @@ void ExeDepsFix::visitInstr(MachineInstr *MI) {
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visitHardInstr(MI, DomP.first);
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}
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// Process defs to track register ages, and kill values clobbered by generic
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// instructions.
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processDefs(MI, !DomP.first);
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return !DomP.first;
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}
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/// \brief Helps avoid false dependencies on undef registers by updating the
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@ -542,14 +558,7 @@ bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
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DEBUG(dbgs() << ": Break dependency.\n");
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continue;
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}
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// The current clearance seems OK, but we may be ignoring a def from a
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// back-edge.
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if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
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DEBUG(dbgs() << ": OK .\n");
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return false;
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}
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// A def from an unprocessed back-edge may make us break this dependency.
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DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
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DEBUG(dbgs() << ": OK .\n");
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return false;
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}
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return true;
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@ -559,16 +568,19 @@ bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
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// If Kill is set, also kill off DomainValues clobbered by the defs.
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//
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// Also break dependencies on partial defs and undef uses.
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void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
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void ExeDepsFix::processDefs(MachineInstr *MI, bool breakDependency,
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bool Kill) {
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assert(!MI->isDebugValue() && "Won't process debug values");
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// Break dependence on undef uses. Do this before updating LiveRegs below.
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unsigned OpNum;
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unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
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if (Pref) {
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pickBestRegisterForUndef(MI, OpNum, Pref);
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if (shouldBreakDependence(MI, OpNum, Pref))
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UndefReads.push_back(std::make_pair(MI, OpNum));
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if (breakDependency) {
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unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
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if (Pref) {
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pickBestRegisterForUndef(MI, OpNum, Pref);
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if (shouldBreakDependence(MI, OpNum, Pref))
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UndefReads.push_back(std::make_pair(MI, OpNum));
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}
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}
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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@ -584,11 +596,13 @@ void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
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DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
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<< '\t' << *MI);
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// Check clearance before partial register updates.
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// Call breakDependence before setting LiveRegs[rx].Def.
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unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
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if (Pref && shouldBreakDependence(MI, i, Pref))
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TII->breakPartialRegDependency(*MI, i, TRI);
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if (breakDependency) {
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// Check clearance before partial register updates.
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// Call breakDependence before setting LiveRegs[rx].Def.
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unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
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if (Pref && shouldBreakDependence(MI, i, Pref))
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TII->breakPartialRegDependency(*MI, i, TRI);
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}
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// How many instructions since rx was last written?
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LiveRegs[rx].Def = CurInstr;
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@ -780,6 +794,52 @@ void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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}
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}
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void ExeDepsFix::processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass) {
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enterBasicBlock(MBB);
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// If this block is not done, it makes little sense to make any decisions
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// based on clearance information. We need to make a second pass anyway,
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// and by then we'll have better information, so we can avoid doing the work
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// to try and break dependencies now.
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bool breakDependency = isBlockDone(MBB);
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for (MachineInstr &MI : *MBB) {
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if (!MI.isDebugValue()) {
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bool Kill = false;
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if (PrimaryPass)
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Kill = visitInstr(&MI);
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processDefs(&MI, breakDependency, Kill);
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}
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}
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if (breakDependency)
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processUndefReads(MBB);
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leaveBasicBlock(MBB);
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}
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bool ExeDepsFix::isBlockDone(MachineBasicBlock *MBB) {
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return MBBInfos[MBB].PrimaryCompleted &&
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MBBInfos[MBB].IncomingCompleted == MBBInfos[MBB].PrimaryIncoming &&
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MBBInfos[MBB].IncomingProcessed == MBB->pred_size();
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}
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void ExeDepsFix::updateSuccessors(MachineBasicBlock *MBB, bool Primary) {
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bool Done = isBlockDone(MBB);
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for (auto *Succ : MBB->successors()) {
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if (!isBlockDone(Succ)) {
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if (Primary) {
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MBBInfos[Succ].IncomingProcessed++;
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}
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if (Done) {
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MBBInfos[Succ].IncomingCompleted++;
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}
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if (isBlockDone(Succ)) {
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// Perform secondary processing for this successor. See the big comment
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// in runOnMachineFunction, for an explanation of the iteration order.
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processBasicBlock(Succ, false);
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updateSuccessors(Succ, false);
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}
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}
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}
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}
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bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
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if (skipFunction(*mf.getFunction()))
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return false;
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@ -816,44 +876,80 @@ bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
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AliasMap[*AI].push_back(i);
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}
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// Initialize the MMBInfos
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for (auto &MBB : mf) {
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MBBInfo InitialInfo;
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MBBInfos.insert(std::make_pair(&MBB, InitialInfo));
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}
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/*
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* We want to visit every instruction in every basic block in order to update
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* it's execution domain or break any false dependencies. However, for the
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* dependency breaking, we need to know clearances from all predecessors
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* (including any backedges). One way to do so would be to do two complete
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* passes over all basic blocks/instructions, the first for recording
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* clearances, the second to break the dependencies. However, for functions
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* without backedges, or functions with a lot of straight-line code, and
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* a small loop, that would be a lot of unnecessary work (since only the
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* BBs that are part of the loop require two passes). As an example,
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* consider the following loop.
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*
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*
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* PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
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* ^ |
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* +----------------------------------+
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*
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* The iteration order is as follows:
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* Naive: PH A B C D A' B' C' D'
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* Optimized: PH A B C A' B' C' D
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*
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* Note that we avoid processing D twice, because we can entirely process
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* the predecessors before getting to D. We call a block that is ready
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* for its second round of processing `done` (isBlockDone). Once we finish
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* processing some block, we update the counters in MBBInfos and re-process
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* any successors that are now done.
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*/
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MachineBasicBlock *Entry = &*MF->begin();
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ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
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SmallVector<MachineBasicBlock*, 16> Loops;
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for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
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MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
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MachineBasicBlock *MBB = *MBBI;
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enterBasicBlock(MBB);
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if (SeenUnknownBackEdge)
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Loops.push_back(MBB);
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for (MachineInstr &MI : *MBB)
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visitInstr(&MI);
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processUndefReads(MBB);
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leaveBasicBlock(MBB);
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// N.B: IncomingProcessed and IncomingCompleted were already updated while
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// processing this block's predecessors.
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MBBInfos[MBB].PrimaryCompleted = true;
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MBBInfos[MBB].PrimaryIncoming = MBBInfos[MBB].IncomingProcessed;
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processBasicBlock(MBB, true);
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updateSuccessors(MBB, true);
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}
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// Visit all the loop blocks again in order to merge DomainValues from
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// back-edges.
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for (MachineBasicBlock *MBB : Loops) {
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enterBasicBlock(MBB);
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for (MachineInstr &MI : *MBB)
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if (!MI.isDebugValue())
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processDefs(&MI, false);
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processUndefReads(MBB);
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leaveBasicBlock(MBB);
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// We need to go through again and finalize any blocks that are not done yet.
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// This is possible if blocks have dead predecessors, so we didn't visit them
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// above.
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for (ReversePostOrderTraversal<MachineBasicBlock *>::rpo_iterator
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MBBI = RPOT.begin(),
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MBBE = RPOT.end();
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MBBI != MBBE; ++MBBI) {
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MachineBasicBlock *MBB = *MBBI;
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if (!isBlockDone(MBB)) {
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processBasicBlock(MBB, false);
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// Don't update successors here. We'll get to them anyway through this
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// loop.
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}
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}
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// Clear the LiveOuts vectors and collapse any remaining DomainValues.
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for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
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MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
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LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
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if (FI == LiveOuts.end() || !FI->second)
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auto FI = MBBInfos.find(*MBBI);
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if (FI == MBBInfos.end() || !FI->second.OutRegs)
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continue;
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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if (FI->second[i].Value)
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release(FI->second[i].Value);
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delete[] FI->second;
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if (FI->second.OutRegs[i].Value)
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release(FI->second.OutRegs[i].Value);
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delete[] FI->second.OutRegs;
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}
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LiveOuts.clear();
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MBBInfos.clear();
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UndefReads.clear();
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Avail.clear();
|
||||
Allocator.DestroyAll();
|
||||
|
||||
@ -277,3 +277,60 @@ ret:
|
||||
;AVX: vcvtsi2sdq {{.*}}, [[XMM4_7:%xmm[4-7]]], {{%xmm[0-9]+}}
|
||||
;AVX-NOT: [[XMM4_7]]
|
||||
}
|
||||
|
||||
; Make sure we are making a smart choice regarding undef registers even for more
|
||||
; complicated loop structures. This example is the inner loop from
|
||||
; julia> a = falses(10000); a[1:4:end] = true
|
||||
; julia> linspace(1.0,2.0,10000)[a]
|
||||
define void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c2, double %c3, double %c4, i64 %size) {
|
||||
entry:
|
||||
tail call void asm sideeffect "", "~{xmm7},~{dirflag},~{fpsr},~{flags}"()
|
||||
tail call void asm sideeffect "", "~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{dirflag},~{fpsr},~{flags}"()
|
||||
tail call void asm sideeffect "", "~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%phi_i = phi i64 [ 1, %entry ], [ %nexti, %loop_end ]
|
||||
%phi_j = phi i64 [ 1, %entry ], [ %nextj, %loop_end ]
|
||||
%phi_k = phi i64 [ 0, %entry ], [ %nextk, %loop_end ]
|
||||
br label %inner_loop
|
||||
|
||||
inner_loop:
|
||||
%phi = phi i64 [ %phi_k, %loop ], [ %nextk, %inner_loop ]
|
||||
%idx = lshr i64 %phi, 6
|
||||
%inputptr = getelementptr i64, i64* %x, i64 %idx
|
||||
%input = load i64, i64* %inputptr, align 8
|
||||
%masked = and i64 %phi, 63
|
||||
%shiftedmasked = shl i64 1, %masked
|
||||
%maskedinput = and i64 %input, %shiftedmasked
|
||||
%cmp = icmp eq i64 %maskedinput, 0
|
||||
%nextk = add i64 %phi, 1
|
||||
br i1 %cmp, label %inner_loop, label %loop_end
|
||||
|
||||
loop_end:
|
||||
%nexti = add i64 %phi_i, 1
|
||||
%nextj = add i64 %phi_j, 1
|
||||
; Register use, plus us clobbering 7-15 above, basically forces xmm6 here as
|
||||
; the only reasonable choice. The primary thing we care about is that it's
|
||||
; not one of the registers used in the loop (e.g. not the output reg here)
|
||||
;AVX-NOT: %xmm6
|
||||
;AVX: vcvtsi2sdq {{.*}}, %xmm6, {{%xmm[0-9]+}}
|
||||
;AVX-NOT: %xmm6
|
||||
%nexti_f = sitofp i64 %nexti to double
|
||||
%sub = fsub double %c1, %nexti_f
|
||||
%mul = fmul double %sub, %c2
|
||||
;AVX: vcvtsi2sdq {{.*}}, %xmm6, {{%xmm[0-9]+}}
|
||||
;AVX-NOT: %xmm6
|
||||
%phi_f = sitofp i64 %phi to double
|
||||
%mul2 = fmul double %phi_f, %c3
|
||||
%add2 = fadd double %mul, %mul2
|
||||
%div = fdiv double %add2, %c4
|
||||
%prev_j = add i64 %phi_j, -1
|
||||
%outptr = getelementptr double, double* %y, i64 %prev_j
|
||||
store double %div, double* %outptr, align 8
|
||||
%done = icmp slt i64 %size, %nexti
|
||||
br i1 %done, label %loopdone, label %loop
|
||||
|
||||
loopdone:
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user