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[x86] Fix AVX maskload/store intrinsic prototypes.
The mask value type for maskload/maskstore GCC builtins is never a vector of packed floats/doubles. This patch fixes the following issues: 1. The mask argument for builtin_ia32_maskloadpd and builtin_ia32_maskstorepd should be of type llvm_v2i64_ty and not llvm_v2f64_ty. 2. The mask argument for builtin_ia32_maskloadpd256 and builtin_ia32_maskstorepd256 should be of type llvm_v4i64_ty and not llvm_v4f64_ty. 3. The mask argument for builtin_ia32_maskloadps and builtin_ia32_maskstoreps should be of type llvm_v4i32_ty and not llvm_v4f32_ty. 4. The mask argument for builtin_ia32_maskloadps256 and builtin_ia32_maskstoreps256 should be of type llvm_v8i32_ty and not llvm_v8f32_ty. Differential Revision: http://reviews.llvm.org/D13776 llvm-svn: 250817
This commit is contained in:
Andrea Di Biagio
parent
d46cdf8cd0
commit
4de2e09295
@ -1760,16 +1760,16 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Conditional load ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx_maskload_pd : GCCBuiltin<"__builtin_ia32_maskloadpd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty],
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Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2i64_ty],
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[IntrReadArgMem]>;
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def int_x86_avx_maskload_ps : GCCBuiltin<"__builtin_ia32_maskloadps">,
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Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty],
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Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4i32_ty],
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[IntrReadArgMem]>;
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def int_x86_avx_maskload_pd_256 : GCCBuiltin<"__builtin_ia32_maskloadpd256">,
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty],
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4i64_ty],
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[IntrReadArgMem]>;
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def int_x86_avx_maskload_ps_256 : GCCBuiltin<"__builtin_ia32_maskloadps256">,
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty],
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8i32_ty],
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[IntrReadArgMem]>;
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def int_x86_avx512_mask_loadu_ps_512 : GCCBuiltin<"__builtin_ia32_loadups512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty],
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@ -1789,18 +1789,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v2f64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;
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llvm_v2i64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;
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def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v4f32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;
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llvm_v4i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;
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def int_x86_avx_maskstore_pd_256 :
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GCCBuiltin<"__builtin_ia32_maskstorepd256">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v4f64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
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llvm_v4i64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
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def int_x86_avx_maskstore_ps_256 :
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GCCBuiltin<"__builtin_ia32_maskstoreps256">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v8f32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
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llvm_v8i32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
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def int_x86_avx512_mask_storeu_ps_512 :
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GCCBuiltin<"__builtin_ia32_storeups512_mask">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v16f32_ty, llvm_i16_ty],
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@ -2536,102 +2536,102 @@ define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
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declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
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define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {
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define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) {
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; CHECK-LABEL: test_x86_avx_maskload_pd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovpd (%eax), %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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%res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x double>) nounwind readonly
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declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>) nounwind readonly
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define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x double> %a1) {
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define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) {
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; CHECK-LABEL: test_x86_avx_maskload_pd_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovpd (%eax), %ymm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
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%res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1]
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x double>) nounwind readonly
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declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>) nounwind readonly
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define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x float> %a1) {
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define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) {
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; CHECK-LABEL: test_x86_avx_maskload_ps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovps (%eax), %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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%res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x float>) nounwind readonly
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declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x i32>) nounwind readonly
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define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x float> %a1) {
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define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) {
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; CHECK-LABEL: test_x86_avx_maskload_ps_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovps (%eax), %ymm0, %ymm0
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; CHECK-NEXT: retl
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%res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
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%res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind readonly
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) nounwind readonly
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define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x double> %a1, <2 x double> %a2) {
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define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) {
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; CHECK-LABEL: test_x86_avx_maskstore_pd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovpd %xmm1, %xmm0, (%eax)
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; CHECK-NEXT: retl
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call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x double> %a1, <2 x double> %a2)
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call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2)
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ret void
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}
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declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x double>, <2 x double>) nounwind
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declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>) nounwind
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define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x double> %a1, <4 x double> %a2) {
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define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) {
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; CHECK-LABEL: test_x86_avx_maskstore_pd_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovpd %ymm1, %ymm0, (%eax)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retl
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call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x double> %a1, <4 x double> %a2)
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call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x i64> %mask, <4 x double> %a2)
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ret void
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}
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declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x double>, <4 x double>) nounwind
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declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>) nounwind
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define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x float> %a1, <4 x float> %a2) {
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define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) {
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; CHECK-LABEL: test_x86_avx_maskstore_ps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovps %xmm1, %xmm0, (%eax)
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; CHECK-NEXT: retl
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call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x float> %a1, <4 x float> %a2)
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call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2)
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ret void
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}
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declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x float>, <4 x float>) nounwind
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declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>) nounwind
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define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x float> %a1, <8 x float> %a2) {
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define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) {
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; CHECK-LABEL: test_x86_avx_maskstore_ps_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vmaskmovps %ymm1, %ymm0, (%eax)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retl
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call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x float> %a1, <8 x float> %a2)
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call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x i32> %mask, <8 x float> %a2)
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ret void
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}
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
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define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {
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@ -88,7 +88,7 @@ entry:
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ret void
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}
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
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; CHECK_O0: _f_f
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; CHECK-O0: vmovss LCPI
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@ -105,7 +105,7 @@ cif_mask_mixed: ; preds = %allocas
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br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check
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cif_mixed_test_all: ; preds = %cif_mask_mixed
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call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <8 x float> undef) nounwind
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call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x i32> <i32 -1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <8 x float> undef) nounwind
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unreachable
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cif_mixed_test_any_check: ; preds = %cif_mask_mixed
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@ -42,6 +42,4 @@ safe_if_after_false: ; preds = %safe_if_run_false,
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}
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declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x float>) nounwind readonly
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
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