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Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"

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This reverts commit c1b3716614bc0a107e6f41a7d3d503baefad8a5b.

llvm-svn: 361918
This commit is contained in:
Pengfei Wang 2019-05-29 02:49:59 +00:00
parent 34db7d178c
commit 4e2174e643
2 changed files with 4 additions and 6 deletions
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4
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
View File

@ -91,9 +91,7 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
return RB; return RB;
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>()) if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
return &getRegBankFromRegClass(*RC); return &getRegBankFromRegClass(*RC);
return nullptr;
llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "
"a const TargetRegisterClass*");
} }
const TargetRegisterClass & const TargetRegisterClass &

6
lib/Target/X86/X86InstructionSelector.cpp
View File

@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
"Arguments and return value types must match"); "Arguments and return value types must match");
const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI); const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
if (RegRB.getID() != X86::GPRRegBankID) if (!RegRB || RegRB->getID() != X86::GPRRegBankID)
return false; return false;
const static unsigned NumTypes = 4; // i8, i16, i32, i64 const static unsigned NumTypes = 4; // i8, i16, i32, i64
@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
const DivRemEntry &TypeEntry = *OpEntryIt; const DivRemEntry &TypeEntry = *OpEntryIt;
const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB); const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
!RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
!RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {