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Add support for CPU features (i.e., bugs) and workarounds.
This is just the framework to identify the needed workarounds. They are not actually implemented. llvm-svn: 77902
This commit is contained in:
Jakob Stoklund Olesen
parent
5c6e03f669
commit
4e31b23a32
@ -20,8 +20,53 @@ include "llvm/Target/Target.td"
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// Blackfin Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSSYNC : SubtargetFeature<"ssync","ssyncWorkaround", "true",
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"Work around SSYNC bugs">;
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def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true",
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"Build for SDRAM">;
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def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true",
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"Assume instruction cache lookaside buffers are enabled at runtime">;
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//===----------------------------------------------------------------------===//
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// Bugs in the silicon becomes workarounds in the compiler.
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// See http://www.analog.com/ for the full list of IC anomalies.
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//===----------------------------------------------------------------------===//
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def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true",
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"Work around 05000074 - "
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"Multi-Issue Instruction with dsp32shiftimm and P-reg Store">;
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def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true",
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"Work around 05000244 - "
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"If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">;
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def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true",
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"Work around 05000245 - "
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"Access in the Shadow of a Conditional Branch">;
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def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true",
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"Work around 05000257 - "
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"Interrupt/Exception During Short Hardware Loop">;
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def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true",
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"Work around 05000283 - "
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"System MMR Write Is Stalled Indefinitely when Killed">;
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def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true",
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"Work around 05000312 - "
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"SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">;
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def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly",
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"wa_killed_mmr", "true",
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"Work around 05000315 - "
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"Killed System MMR Write Completes Erroneously on Next System MMR Access">;
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def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true",
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"Work around 05000371 - "
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"Possible RETS Register Corruption when Subroutine Is under 5 Cycles">;
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def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true",
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"Work around 05000426 - "
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"Speculative Fetches of Indirect-Pointer Instructions">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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@ -37,10 +82,114 @@ def BlackfinInstrInfo : InstrInfo {}
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// Blackfin processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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class Proc<string Name, string Suffix, list<SubtargetFeature> Features>
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: Processor<!strconcat(Name, Suffix), NoItineraries, Features>;
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def : Proc<"generic", [FeatureSSYNC]>;
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def : Proc<"generic", "", []>;
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multiclass Core<string Name,string Suffix,
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list<SubtargetFeature> Features> {
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def : Proc<Name, Suffix, Features>;
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def : Proc<Name, "", Features>;
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def : Proc<Name, "-none", []>;
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}
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multiclass CoreEdinburgh<string Name>
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: Core<Name, "-0.6", [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS]> {
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def : Proc<Name, "-0.5",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS]>;
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def : Proc<Name, "-0.4",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS]>;
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}
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multiclass CoreBraemar<string Name>
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: Core<Name, "-0.3",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]> {
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def : Proc<Name, "-0.2",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreStirling<string Name>
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: Core<Name, "-0.5", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.4",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreMoab<string Name>
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: Core<Name, "-0.3", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.0",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreTeton<string Name>
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: Core<Name, "-0.5",
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[WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
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WA_RETS, WA_IND_CALL]> {
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def : Proc<Name, "-0.3",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any",
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[WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
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WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreKookaburra<string Name>
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: Core<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
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}
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multiclass CoreMockingbird<string Name>
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: Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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}
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multiclass CoreBrodie<string Name>
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: Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
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def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
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}
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defm BF512 : CoreBrodie<"bf512">;
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defm BF514 : CoreBrodie<"bf514">;
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defm BF516 : CoreBrodie<"bf516">;
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defm BF518 : CoreBrodie<"bf518">;
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defm BF522 : CoreMockingbird<"bf522">;
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defm BF523 : CoreKookaburra<"bf523">;
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defm BF524 : CoreMockingbird<"bf524">;
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defm BF525 : CoreKookaburra<"bf525">;
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defm BF526 : CoreMockingbird<"bf526">;
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defm BF527 : CoreKookaburra<"bf527">;
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defm BF531 : CoreEdinburgh<"bf531">;
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defm BF532 : CoreEdinburgh<"bf532">;
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defm BF533 : CoreEdinburgh<"bf533">;
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defm BF534 : CoreBraemar<"bf534">;
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defm BF536 : CoreBraemar<"bf536">;
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defm BF537 : CoreBraemar<"bf537">;
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defm BF538 : CoreStirling<"bf538">;
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defm BF539 : CoreStirling<"bf539">;
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defm BF542 : CoreMoab<"bf542">;
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defm BF544 : CoreMoab<"bf544">;
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defm BF548 : CoreMoab<"bf548">;
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defm BF549 : CoreMoab<"bf549">;
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defm BF561 : CoreTeton<"bf561">;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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@ -18,9 +18,20 @@ using namespace llvm;
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BlackfinSubtarget::BlackfinSubtarget(const TargetMachine &TM,
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const Module &M,
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const std::string &FS) {
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const std::string &FS)
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: sdram(false),
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icplb(false),
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wa_mi_shift(false),
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wa_csync(false),
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wa_specld(false),
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wa_mmr_stall(false),
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wa_lcregs(false),
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wa_hwloop(false),
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wa_ind_call(false),
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wa_killed_mmr(false),
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wa_rets(false)
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{
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std::string CPU = "generic";
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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}
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@ -23,7 +23,17 @@ namespace llvm {
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class Module;
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class BlackfinSubtarget : public TargetSubtarget {
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bool ssyncWorkaround;
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bool sdram;
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bool icplb;
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bool wa_mi_shift;
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bool wa_csync;
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bool wa_specld;
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bool wa_mmr_stall;
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bool wa_lcregs;
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bool wa_hwloop;
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bool wa_ind_call;
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bool wa_killed_mmr;
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bool wa_rets;
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public:
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BlackfinSubtarget(const TargetMachine &TM, const Module &M,
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const std::string &FS);
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@ -170,3 +170,75 @@ Stores:
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| I-- | * | | * | * | |
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| I++M | * | | | | |
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* Workarounds and features
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Blackfin CPUs have bugs. Each model comes in a number of silicon revisions with
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different bugs. We learn about the CPU model from the -mcpu switch.
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** Interpretation of -mcpu value
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- -mcpu=bf527 refers to the latest known BF527 revision
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- -mcpu=bf527-0.2 refers to silicon rev. 0.2
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- -mcpu=bf527-any refers to all known revisions
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- -mcpu=bf527-none disables all workarounds
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The -mcpu setting affects the __SILICON_REVISION__ macro and enabled workarounds:
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| -mcpu | __SILICON_REVISION__ | Workarounds |
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|------------+----------------------+--------------------|
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| bf527 | Def Latest | Specific to latest |
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| bf527-1.3 | Def 0x0103 | Specific to 1.3 |
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| bf527-any | Def 0xffff | All bf527-x.y |
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| bf527-none | Undefined | None |
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These are the known cores and revisions:
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| Core | Silicon | Processors |
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|-------------+--------------------+-------------------------|
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| Edinburgh | 0.3, 0.4, 0.5, 0.6 | BF531 BF532 BF533 |
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| Braemar | 0.2, 0.3 | BF534 BF536 BF537 |
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| Stirling | 0.3, 0.4, 0.5 | BF538 BF539 |
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| Moab | 0.0, 0.1, 0.2 | BF542 BF544 BF548 BF549 |
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| Teton | 0.3, 0.5 | BF561 |
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| Kookaburra | 0.0, 0.1, 0.2 | BF523 BF525 BF527 |
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| Mockingbird | 0.0, 0.1 | BF522 BF524 BF526 |
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| Brodie | 0.0, 0.1 | BF512 BF514 BF516 BF518 |
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** Compiler implemented workarounds
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Most workarounds are implemented in header files and source code using the
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__ADSPBF527__ macros. A few workarounds require compiler support.
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| Anomaly | Macro | GCC Switch |
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|----------+--------------------------------+------------------|
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| Any | __WORKAROUNDS_ENABLED | |
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| 05000074 | WA_05000074 | |
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| 05000244 | __WORKAROUND_SPECULATIVE_SYNCS | -mcsync-anomaly |
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| 05000245 | __WORKAROUND_SPECULATIVE_LOADS | -mspecld-anomaly |
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| 05000257 | WA_05000257 | |
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| 05000283 | WA_05000283 | |
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| 05000312 | WA_LOAD_LCREGS | |
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| 05000315 | WA_05000315 | |
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| 05000371 | __WORKAROUND_RETS | |
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| 05000426 | __WORKAROUND_INDIRECT_CALLS | Not -micplb |
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** GCC feature switches
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| Switch | Description |
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|---------------------------+----------------------------------------|
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| -msim | Use simulator runtime |
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| -momit-leaf-frame-pointer | Omit frame pointer for leaf functions |
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| -mlow64k | |
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| -mcsync-anomaly | |
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| -mspecld-anomaly | |
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| -mid-shared-library | |
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| -mleaf-id-shared-library | |
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| -mshared-library-id= | |
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| -msep-data | Enable separate data segment |
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| -mlong-calls | Use indirect calls |
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| -mfast-fp | |
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| -mfdpic | |
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| -minline-plt | |
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| -mstack-check-l1 | Do stack checking in L1 scratch memory |
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| -mmulticore | Enable multicore support |
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| -mcorea | Build for Core A |
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| -mcoreb | Build for Core B |
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| -msdram | Build for SDRAM |
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| -micplb | Assume ICPLBs are enabled at runtime. |
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