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[llvm-mca] Add tests for instructions that implicitly clear the upper portion of a super-register.

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On x86-64, a write to register EAX implicitly clears the upper half or RAX.
128-bit AVX instructions clear the upper 128-bit of the YMM register that
aliases the XMM definition register.

llvm-mca doesn't know about register writes that implicitly clear the upper
portion of an aliasing super-register. This issue will be fixed in a future patch.

llvm-svn: 334742
This commit is contained in:
Andrea Di Biagio 2018-06-14 17:48:42 +00:00
parent c8a450ead2
commit 4f0c283682
2 changed files with 176 additions and 0 deletions
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60
test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s Normal file
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s
## Sets register RAX.
imulq $5, %rcx, %rax
## Kills the previous definition of RAX.
## The upper portion of RAX is cleared.
lzcnt %ecx, %eax
## The AND can start immediately after the LZCNT.
## It doesn't need to wait for the IMUL.
and %rcx, %rax
bsf %rax, %rcx
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 400
# CHECK-NEXT: Total Cycles: 1203
# CHECK-NEXT: Dispatch Width: 2
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 6.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 4.00 imulq $5, %rcx, %rax
# CHECK-NEXT: 1 1 0.50 lzcntl %ecx, %eax
# CHECK-NEXT: 1 1 0.50 andq %rcx, %rax
# CHECK-NEXT: 8 5 2.00 bsfq %rax, %rcx
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0123456
# CHECK: [0,0] DeeeeeeER . . . .. imulq $5, %rcx, %rax
# CHECK-NEXT: [0,1] .DeE----R . . . .. lzcntl %ecx, %eax
# CHECK-NEXT: [0,2] .D=====eER. . . .. andq %rcx, %rax
# CHECK-NEXT: [0,3] . D=====eeeeeER. . .. bsfq %rax, %rcx
# CHECK-NEXT: [1,0] . .D======eeeeeeER .. imulq $5, %rcx, %rax
# CHECK-NEXT: [1,1] . . D=====eE-----R .. lzcntl %ecx, %eax
# CHECK-NEXT: [1,2] . . D===========eER .. andq %rcx, %rax
# CHECK-NEXT: [1,3] . . D===========eeeeeER bsfq %rax, %rcx
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 2 4.0 0.5 0.0 imulq $5, %rcx, %rax
# CHECK-NEXT: 1. 2 3.5 0.5 4.5 lzcntl %ecx, %eax
# CHECK-NEXT: 2. 2 9.0 0.0 0.0 andq %rcx, %rax
# CHECK-NEXT: 3. 2 9.0 0.0 0.0 bsfq %rax, %rcx

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test/tools/llvm-mca/X86/BtVer2/clear-super-register-2.s Normal file
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s
# In this test, the VDIVPS takes 38 cycles to write to register YMM3. The first
# VADDPS does not depend on the VDIVPS (the WAW dependency is eliminated at
# register renaming stage). So the first VADDPS can be executed in parallel to
# the VDIVPS. That VADDPS also writes to register XMM3, and the upper half of
# YMM3 is implicitly cleared. As a consequence, the definition of YMM3 from the
# VDIVPS is killed, and the subsequent VADDPS instructions don't need to wait
# for the VDIVPS to complete.
# The block reciprocal throughput is limited by the VDIVPS reciprocal throughput
# (which is 38 cycles). The sequence of VADDPS can be executed in parallel on
# the FPA unit; their latency is "hidden" by the long latency of the VDIVPS.
vdivps %ymm0, %ymm1, %ymm3
vaddps %xmm0, %xmm1, %xmm3
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vaddps %ymm3, %ymm1, %ymm4
vandps %xmm4, %xmm1, %xmm0
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1800
# CHECK-NEXT: Total Cycles: 7003
# CHECK-NEXT: Dispatch Width: 2
# CHECK-NEXT: IPC: 0.26
# CHECK-NEXT: Block RThroughput: 38.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 38 38.00 vdivps %ymm0, %ymm1, %ymm3
# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm3
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 2 3 2.00 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 1 1 0.50 vandps %xmm4, %xmm1, %xmm0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 01234
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . . vdivps %ymm0, %ymm1, %ymm3
# CHECK-NEXT: [0,1] .DeeeE----------------------------------R . . . . . . . vaddps %xmm0, %xmm1, %xmm3
# CHECK-NEXT: [0,2] . D====================================eeeER . . . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,3] . D=====================================eeeER . . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,4] . D======================================eeeER . . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,5] . D=======================================eeeER. . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,6] . .D========================================eeeER . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,7] . . D=========================================eeeER . . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,8] . . D==========================================eeeER . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,9] . . D===========================================eeeER . . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,10] . . D============================================eeeER. . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,11] . . .D=============================================eeeER . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,12] . . . D==============================================eeeER . . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,13] . . . D===============================================eeeER . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,14] . . . D================================================eeeER . . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,15] . . . D=================================================eeeER. . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,16] . . . .D==================================================eeeER . vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: [0,17] . . . . D====================================================eER . vandps %xmm4, %xmm1, %xmm0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vdivps %ymm0, %ymm1, %ymm3
# CHECK-NEXT: 1. 1 1.0 1.0 34.0 vaddps %xmm0, %xmm1, %xmm3
# CHECK-NEXT: 2. 1 37.0 0.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 3. 1 38.0 2.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 4. 1 39.0 4.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 5. 1 40.0 6.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 6. 1 41.0 8.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 7. 1 42.0 10.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 8. 1 43.0 12.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 9. 1 44.0 14.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 10. 1 45.0 16.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 11. 1 46.0 18.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 12. 1 47.0 20.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 13. 1 48.0 22.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 14. 1 49.0 24.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 15. 1 50.0 26.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 16. 1 51.0 28.0 0.0 vaddps %ymm3, %ymm1, %ymm4
# CHECK-NEXT: 17. 1 53.0 0.0 0.0 vandps %xmm4, %xmm1, %xmm0