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[AArch64] Add command-line option for SB

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SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.

This patch also moves to FeatureSB the old FeatureSpecRestrict.

Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman	

Differential Revision: https://reviews.llvm.org/D55921

llvm-svn: 350126
This commit is contained in:
Diogo N. Sampaio 2018-12-28 17:14:58 +00:00
parent 96863015f8
commit 4f295fed38
9 changed files with 26 additions and 23 deletions
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1
include/llvm/Support/AArch64TargetParser.def
View File

@ -73,6 +73,7 @@ AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME

1
include/llvm/Support/AArch64TargetParser.h
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@ -48,6 +48,7 @@ enum ArchExtKind : unsigned {
AEK_RAND = 1 << 18,
AEK_MTE = 1 << 19,
AEK_SSBS = 1 << 20,
AEK_SB = 1 << 21,
};
enum class ArchKind {

8
lib/Target/AArch64/AArch64.td
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@ -306,12 +306,12 @@ def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction" >;
def FeatureSB : SubtargetFeature<"sb", "HasSB",
"true", "Enable v8.5 Speculation Barrier" >;
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
"true", "Enable Speculative Store Bypass Safe bit" >;
def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
"Enable speculation control barrier" >;
def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
"Enable execution and data prediction invalidation instructions" >;
@ -352,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
FeatureBranchTargetId]
>;

6
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -114,8 +114,8 @@ def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
def HasSB : Predicate<"Subtarget->hasSB()">,
AssemblerPredicate<"FeatureSB", "sb">;
def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
@ -733,7 +733,7 @@ def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> {
def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
let Inst{20-5} = 0b0001100110000111;
let Unpredictable{11-8} = 0b1111;
let Predicates = [HasSpecCtrl];
let Predicates = [HasSB];
let hasSideEffects = 1;
}

4
lib/Target/AArch64/AArch64Subtarget.h
View File

@ -126,8 +126,8 @@ protected:
bool HasAlternativeNZCV = false;
bool HasFRInt3264 = false;
bool HasSpecRestrict = false;
bool HasSpecCtrl = false;
bool HasSSBS = false;
bool HasSB = false;
bool HasPredCtrl = false;
bool HasCCDP = false;
bool HasBTI = false;
@ -355,8 +355,8 @@ public:
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
bool hasFRInt3264() const { return HasFRInt3264; }
bool hasSpecRestrict() const { return HasSpecRestrict; }
bool hasSpecCtrl() const { return HasSpecCtrl; }
bool hasSSBS() const { return HasSSBS; }
bool hasSB() const { return HasSB; }
bool hasPredCtrl() const { return HasPredCtrl; }
bool hasCCDP() const { return HasCCDP; }
bool hasBTI() const { return HasBTI; }

8
test/MC/AArch64/armv8.5a-specctrl.s → test/MC/AArch64/armv8.5a-sb.s
View File

@ -1,11 +1,11 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sb -o - %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a -o - %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-sb -o - %s 2>&1 | FileCheck %s --check-prefix=NOSB
// Flag manipulation
sb
// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
// NOSB: instruction requires: specctrl
// NOSB: instruction requires: sb
// NOSB-NEXT: sb

9
test/MC/Disassembler/AArch64/armv8.5a-sb.txt Normal file
View File

@ -0,0 +1,9 @@
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
# New reg
0xff 0x30 0x03 0xd5
# CHECK: sb
# NOSB: msr S0_3_C3_C0_7, xzr

9
test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt
View File

@ -1,9 +0,0 @@
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
# New reg
0xff 0x30 0x03 0xd5
# CHECK: sb
# NOSB: msr S0_3_C3_C0_7, xzr

3
unittests/Support/TargetParserTest.cpp
View File

@ -988,7 +988,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"rcpc", "norcpc", "+rcpc", "-rcpc" },
{"rng", "norng", "+rand", "-rand"},
{"memtag", "nomemtag", "+mte", "-mte"},
{"ssbs", "nossbs", "+ssbs", "-ssbs"}};
{"ssbs", "nossbs", "+ssbs", "-ssbs"},
{"sb", "nosb", "+sb", "-sb"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),