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use TLI.allowsMemoryAccess() to check if memory accesses are fast; NFCI
This consolidates use of isUnalignedMem32Slow() in one place. There is a slight change in logic although I'm not sure that it would ever come up in the real world: we were assuming that an alignment of the type size is always fast; now, we actually check the data layout to confirm that. llvm-svn: 245382
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@ -24101,10 +24101,13 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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// For chips with slow 32-byte unaligned loads, break the 32-byte operation
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// into two 16-byte operations.
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ISD::LoadExtType Ext = Ld->getExtensionType();
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bool Fast;
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unsigned AddressSpace = Ld->getAddressSpace();
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unsigned Alignment = Ld->getAlignment();
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bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
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if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
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!DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
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if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
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Ext == ISD::NON_EXTLOAD &&
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TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
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AddressSpace, Alignment, &Fast) && !Fast) {
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unsigned NumElems = RegVT.getVectorNumElements();
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if (NumElems < 2)
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return SDValue();
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@ -24318,10 +24321,12 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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// If we are saving a concatenation of two XMM registers and 32-byte stores
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// are slow, such as on Sandy Bridge, perform two 16-byte stores.
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bool Fast;
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unsigned AddressSpace = St->getAddressSpace();
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unsigned Alignment = St->getAlignment();
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bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
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if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
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StVT == VT && !IsAligned) {
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if (VT.is256BitVector() && StVT == VT &&
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TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
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AddressSpace, Alignment, &Fast) && !Fast) {
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unsigned NumElems = VT.getVectorNumElements();
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if (NumElems < 2)
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return SDValue();
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