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llvm-svn: 288036
This commit is contained in:
Daniel Cederman 2016-11-28 15:33:03 +00:00
parent c8a4e33292
commit 517e67b3a9
1 changed files with 0 additions and 1 deletions
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lib/Target/Sparc/SparcRegisterInfo.td
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@ -331,7 +331,6 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32,
(sequence "L%u", 0, 7),
(sequence "O%u", 0, 7))>;
// Should be in the same order as IntRegs.
def IntPair : RegisterClass<"SP", [v2i32], 64,
(add I0_I1, I2_I3, I4_I5, I6_I7,