mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-02 00:16:25 +00:00
AMDGPU: Make v32i8/v64i8 illegal types
Old intrinsics were forcing these, but they have now all been removed. This fixes large i8 vector operations generally being broken. llvm-svn: 258788
This commit is contained in:
Matt Arsenault
parent
b7742acaf4
commit
51a14cbbc7
@ -43,9 +43,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
|
||||
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
|
||||
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
|
||||
|
||||
addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
|
||||
addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
|
||||
|
||||
addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
|
||||
addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
|
||||
|
||||
|
||||
@ -120,7 +120,7 @@ def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
|
||||
>;
|
||||
|
||||
class SDSample<string opcode> : SDNode <opcode,
|
||||
SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
|
||||
SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
|
||||
SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
|
||||
>;
|
||||
|
||||
|
||||
@ -2102,7 +2102,6 @@ let AddedComplexity = 100 in {
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v32i8>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
|
||||
|
||||
@ -2343,34 +2342,34 @@ defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
|
||||
|
||||
/* SIsample for simple 1D texture lookup */
|
||||
def : Pat <
|
||||
(SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
|
||||
(SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
|
||||
(IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
|
||||
(opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
class SampleShadowPattern<SDNode name, MIMG opcode,
|
||||
ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
class SampleShadowArrayPattern<SDNode name, MIMG opcode,
|
||||
ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
@ -2423,22 +2422,22 @@ defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
|
||||
|
||||
/* int_SI_imageload for texture fetches consuming varying address parameters */
|
||||
class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
|
||||
(name addr_type:$addr, v32i8:$rsrc, imm),
|
||||
(name addr_type:$addr, v8i32:$rsrc, imm),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
|
||||
>;
|
||||
|
||||
class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
|
||||
(name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
|
||||
(name addr_type:$addr, v8i32:$rsrc, TEX_ARRAY),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
|
||||
>;
|
||||
|
||||
class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
|
||||
(name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
|
||||
(name addr_type:$addr, v8i32:$rsrc, TEX_MSAA),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
|
||||
>;
|
||||
|
||||
class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
|
||||
(name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
|
||||
(name addr_type:$addr, v8i32:$rsrc, TEX_ARRAY_MSAA),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
|
||||
>;
|
||||
|
||||
@ -2552,12 +2551,8 @@ def : BitConvert <v4i32, v2f64, VReg_128>;
|
||||
|
||||
def : BitConvert <v8f32, v8i32, SReg_256>;
|
||||
def : BitConvert <v8i32, v8f32, SReg_256>;
|
||||
def : BitConvert <v8i32, v32i8, SReg_256>;
|
||||
def : BitConvert <v32i8, v8i32, SReg_256>;
|
||||
def : BitConvert <v8i32, v32i8, VReg_256>;
|
||||
def : BitConvert <v8i32, v8f32, VReg_256>;
|
||||
def : BitConvert <v8f32, v8i32, VReg_256>;
|
||||
def : BitConvert <v32i8, v8i32, VReg_256>;
|
||||
|
||||
def : BitConvert <v16i32, v16f32, VReg_512>;
|
||||
def : BitConvert <v16f32, v16i32, VReg_512>;
|
||||
|
||||
@ -208,7 +208,7 @@ def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)
|
||||
let CopyCost = 2;
|
||||
}
|
||||
|
||||
def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add SGPR_256)> {
|
||||
def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
|
||||
// Requires 4 s_mov_b64 to copy
|
||||
let CopyCost = 4;
|
||||
}
|
||||
@ -236,7 +236,7 @@ def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VG
|
||||
let CopyCost = 4;
|
||||
}
|
||||
|
||||
def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add VGPR_256)> {
|
||||
def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add VGPR_256)> {
|
||||
let CopyCost = 8;
|
||||
}
|
||||
|
||||
|
||||
111
test/CodeGen/AMDGPU/extract-vector-elt-i8.ll
Normal file
111
test/CodeGen/AMDGPU/extract-vector-elt-i8.ll
Normal file
@ -0,0 +1,111 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v1i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v1i8(i8 addrspace(1)* %out, <1 x i8> %foo) #0 {
|
||||
%p0 = extractelement <1 x i8> %foo, i32 0
|
||||
store i8 %p0, i8 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v2i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v2i8(i8 addrspace(1)* %out, <2 x i8> %foo) #0 {
|
||||
%p0 = extractelement <2 x i8> %foo, i32 0
|
||||
%p1 = extractelement <2 x i8> %foo, i32 1
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v3i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v3i8(i8 addrspace(1)* %out, <3 x i8> %foo) #0 {
|
||||
%p0 = extractelement <3 x i8> %foo, i32 0
|
||||
%p1 = extractelement <3 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v4i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v4i8(i8 addrspace(1)* %out, <4 x i8> %foo) #0 {
|
||||
%p0 = extractelement <4 x i8> %foo, i32 0
|
||||
%p1 = extractelement <4 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v8i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v8i8(i8 addrspace(1)* %out, <8 x i8> %foo) #0 {
|
||||
%p0 = extractelement <8 x i8> %foo, i32 0
|
||||
%p1 = extractelement <8 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v16i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v16i8(i8 addrspace(1)* %out, <16 x i8> %foo) #0 {
|
||||
%p0 = extractelement <16 x i8> %foo, i32 0
|
||||
%p1 = extractelement <16 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v32i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v32i8(i8 addrspace(1)* %out, <32 x i8> %foo) #0 {
|
||||
%p0 = extractelement <32 x i8> %foo, i32 0
|
||||
%p1 = extractelement <32 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}extract_vector_elt_v64i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_load_ubyte
|
||||
; SI: buffer_store_byte
|
||||
; SI: buffer_store_byte
|
||||
define void @extract_vector_elt_v64i8(i8 addrspace(1)* %out, <64 x i8> %foo) #0 {
|
||||
%p0 = extractelement <64 x i8> %foo, i32 0
|
||||
%p1 = extractelement <64 x i8> %foo, i32 2
|
||||
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
|
||||
store i8 %p1, i8 addrspace(1)* %out
|
||||
store i8 %p0, i8 addrspace(1)* %out1
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
@ -5,7 +5,7 @@
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -18,7 +18,7 @@ main_body:
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -31,7 +31,7 @@ main_body:
|
||||
;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -44,7 +44,7 @@ main_body:
|
||||
;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -57,7 +57,7 @@ main_body:
|
||||
;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -70,7 +70,7 @@ main_body:
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -83,7 +83,7 @@ main_body:
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -96,7 +96,7 @@ main_body:
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -109,7 +109,7 @@ main_body:
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -124,7 +124,7 @@ main_body:
|
||||
;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -137,7 +137,7 @@ main_body:
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -150,7 +150,7 @@ main_body:
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -163,7 +163,7 @@ main_body:
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -176,7 +176,7 @@ main_body:
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -189,7 +189,7 @@ main_body:
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -202,7 +202,7 @@ main_body:
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -215,7 +215,7 @@ main_body:
|
||||
;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -228,7 +228,7 @@ main_body:
|
||||
;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -243,7 +243,7 @@ main_body:
|
||||
;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -256,7 +256,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -269,7 +269,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -282,7 +282,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -295,7 +295,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -308,7 +308,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -321,7 +321,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -334,7 +334,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -347,7 +347,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -362,7 +362,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -375,7 +375,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -388,7 +388,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -401,7 +401,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -414,7 +414,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -427,7 +427,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -440,7 +440,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -453,7 +453,7 @@ main_body:
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
@ -464,44 +464,44 @@ main_body:
|
||||
|
||||
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
@ -16,7 +16,7 @@ main_body:
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
@ -27,7 +27,7 @@ main_body:
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod_v4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
@ -35,9 +35,9 @@ main_body:
|
||||
}
|
||||
|
||||
|
||||
declare <4 x float> @llvm.SI.getlod.i32(i32, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user