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[AMDGPU] Add an experimental buffer fat pointer address space.
Add an experimental buffer fat pointer address space that is currently unhandled in the backend. This commit reserves address space 7 as a non-integral pointer repsenting the 160-bit fat pointer (128-bit buffer descriptor + 32-bit offset) that is heavily used in graphics workloads using the AMDGPU backend. Differential Revision: https://reviews.llvm.org/D58957 llvm-svn: 356373
This commit is contained in:
Neil Henning
parent
f777e4c74e
commit
51a5ec492f
@ -281,9 +281,9 @@ LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).
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.. table:: Address Space Mapping
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:name: amdgpu-address-space-mapping-table
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================== =================
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================== =================================
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LLVM Address Space Memory Space
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================== =================
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================== =================================
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0 Generic (Flat)
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1 Global
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2 Region (GDS)
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@ -291,7 +291,15 @@ LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).
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4 Constant
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5 Private (Scratch)
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6 Constant 32-bit
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================== =================
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7 Buffer Fat Pointer (experimental)
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================== =================================
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The buffer fat pointer is an experimental address space that is currently
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unsupported in the backend. It exposes a non-integral pointer that is in future
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intended to support the modelling of 128-bit buffer descriptors + a 32-bit
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offset into the buffer descriptor (in total encapsulating a 160-bit 'pointer'),
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allowing us to use normal LLVM load/store/atomic operations to model the buffer
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descriptors used heavily in graphics workloads targeting the backend.
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.. _amdgpu-memory-scopes:
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@ -245,21 +245,23 @@ enum TargetIndex {
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namespace AMDGPUAS {
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enum : unsigned {
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// The maximum value for flat, generic, local, private, constant and region.
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MAX_AMDGPU_ADDRESS = 6,
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MAX_AMDGPU_ADDRESS = 7,
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FLAT_ADDRESS = 0, ///< Address space for flat memory.
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GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
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REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
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CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
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CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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PRIVATE_ADDRESS = 5, ///< Address space for private memory.
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CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
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CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
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/// Address space for direct addressible parameter memory (CONST0)
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BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
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/// Address space for direct addressible parameter memory (CONST0).
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PARAM_D_ADDRESS = 6,
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/// Address space for indirect addressible parameter memory (VTX1)
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/// Address space for indirect addressible parameter memory (VTX1).
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PARAM_I_ADDRESS = 7,
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// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
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@ -53,20 +53,21 @@ void AMDGPUAAWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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}
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// These arrays are indexed by address space value enum elements 0 ... to 6
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static const AliasResult ASAliasRules[7][7] = {
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/* Flat Global Region Group Constant Private Constant 32-bit */
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/* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias},
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/* Global */ {MayAlias, MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , MayAlias},
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/* Region */ {MayAlias, NoAlias , NoAlias , NoAlias, MayAlias, NoAlias , MayAlias},
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/* Group */ {MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , NoAlias , NoAlias},
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/* Constant */ {MayAlias, MayAlias, MayAlias, NoAlias , NoAlias, NoAlias , MayAlias},
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/* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , NoAlias , MayAlias, NoAlias},
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/* Constant 32-bit */ {MayAlias, MayAlias, MayAlias, NoAlias , MayAlias, NoAlias , NoAlias}
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// These arrays are indexed by address space value enum elements 0 ... to 7
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static const AliasResult ASAliasRules[8][8] = {
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/* Flat Global Region Group Constant Private Constant 32-bit Buffer Fat Ptr */
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/* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias},
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/* Global */ {MayAlias, MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , MayAlias, MayAlias},
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/* Region */ {MayAlias, NoAlias , NoAlias , NoAlias , MayAlias, NoAlias , MayAlias, NoAlias},
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/* Group */ {MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , NoAlias , NoAlias , NoAlias},
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/* Constant */ {MayAlias, MayAlias, MayAlias, NoAlias , NoAlias , NoAlias , MayAlias, MayAlias},
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/* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , NoAlias , MayAlias, NoAlias , NoAlias},
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/* Constant 32-bit */ {MayAlias, MayAlias, MayAlias, NoAlias , MayAlias, NoAlias , NoAlias , MayAlias},
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/* Buffer Fat Ptr */ {MayAlias, MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , MayAlias, MayAlias}
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};
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static AliasResult getAliasResult(unsigned AS1, unsigned AS2) {
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static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 6, "Addr space out of range");
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static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 7, "Addr space out of range");
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if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
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return MayAlias;
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@ -295,10 +295,11 @@ static StringRef computeDataLayout(const Triple &TT) {
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}
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// 32-bit private, local, and region pointers. 64-bit global, constant and
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// flat.
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// flat, non-integral buffer fat pointers.
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return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
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"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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"-ni:7";
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}
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LLVM_READNONE
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@ -253,7 +253,8 @@ unsigned GCNTTIImpl::getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
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if (AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ||
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AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
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AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
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AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
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AddrSpace == AMDGPUAS::BUFFER_FAT_POINTER) {
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return 512;
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}
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@ -1046,7 +1046,8 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
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return isLegalGlobalAddressingMode(AM);
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if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
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AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
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AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
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AS == AMDGPUAS::BUFFER_FAT_POINTER) {
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// If the offset isn't a multiple of 4, it probably isn't going to be
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// correctly aligned.
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// FIXME: Can we get the real alignment here?
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@ -50,3 +50,43 @@ define void @test_1_999(i8 addrspace(1)* %p, i8 addrspace(999)* %p1) {
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define void @test_999_1(i8 addrspace(999)* %p, i8 addrspace(1)* %p1) {
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ret void
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}
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; CHECK: MayAlias: i8 addrspace(7)* %p, i8* %p1
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define void @test_7_0(i8 addrspace(7)* %p, i8 addrspace(0)* %p1) {
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ret void
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}
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; CHECK: MayAlias: i8 addrspace(1)* %p1, i8 addrspace(7)* %p
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define void @test_7_1(i8 addrspace(7)* %p, i8 addrspace(1)* %p1) {
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ret void
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}
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; CHECK: NoAlias: i8 addrspace(2)* %p1, i8 addrspace(7)* %p
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define void @test_7_2(i8 addrspace(7)* %p, i8 addrspace(2)* %p1) {
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ret void
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}
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; CHECK: NoAlias: i8 addrspace(3)* %p1, i8 addrspace(7)* %p
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define void @test_7_3(i8 addrspace(7)* %p, i8 addrspace(3)* %p1) {
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ret void
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}
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; CHECK: MayAlias: i8 addrspace(4)* %p1, i8 addrspace(7)* %p
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define void @test_7_4(i8 addrspace(7)* %p, i8 addrspace(4)* %p1) {
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ret void
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}
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; CHECK: NoAlias: i8 addrspace(5)* %p1, i8 addrspace(7)* %p
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define void @test_7_5(i8 addrspace(7)* %p, i8 addrspace(5)* %p1) {
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ret void
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}
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; CHECK: MayAlias: i8 addrspace(6)* %p1, i8 addrspace(7)* %p
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define void @test_7_6(i8 addrspace(7)* %p, i8 addrspace(6)* %p1) {
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ret void
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}
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; CHECK: MayAlias: i8 addrspace(7)* %p, i8 addrspace(7)* %p1
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define void @test_7_7(i8 addrspace(7)* %p, i8 addrspace(7)* %p1) {
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ret void
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}
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@ -1,7 +1,6 @@
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; RUN: opt -mtriple=r600-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
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; CHECK: MayAlias: i8 addrspace(5)* %p, i8 addrspace(7)* %p1
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define amdgpu_kernel void @test(i8 addrspace(5)* %p, i8 addrspace(7)* %p1) {
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; CHECK: MayAlias: i8 addrspace(5)* %p, i8 addrspace(999)* %p1
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define amdgpu_kernel void @test(i8 addrspace(5)* %p, i8 addrspace(999)* %p1) {
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ret void
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}
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17
test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
Normal file
17
test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
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@ -0,0 +1,17 @@
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; RUN: opt -S -mtriple=amdgcn-- -load-store-vectorizer < %s | FileCheck -check-prefix=OPT %s
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; OPT-LABEL: @func(
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define void @func(i32 addrspace(7)* %out) {
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entry:
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%a0 = getelementptr i32, i32 addrspace(7)* %out, i32 0
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%a1 = getelementptr i32, i32 addrspace(7)* %out, i32 1
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%a2 = getelementptr i32, i32 addrspace(7)* %out, i32 2
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%a3 = getelementptr i32, i32 addrspace(7)* %out, i32 3
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; OPT: store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> addrspace(7)* %0, align 4
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store i32 0, i32 addrspace(7)* %a0
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store i32 1, i32 addrspace(7)* %a1
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store i32 2, i32 addrspace(7)* %a2
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store i32 3, i32 addrspace(7)* %a3
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ret void
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}
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