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[InterleavedAccessPass] Don't increase the number of bytes loaded.
Even if the interleaving transform would otherwise be legal, we shouldn't introduce an interleaved load that is wider than the original load: it might have undefined behavior. It might be possible to perform some sort of mask-narrowing transform in some cases (using a narrower interleaved load, then extending the results using shufflevectors). But I haven't tried to implement that, at least for now. Fixes https://bugs.llvm.org/show_bug.cgi?id=41245 . Differential Revision: https://reviews.llvm.org/D59954 llvm-svn: 357212
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@ -163,14 +163,19 @@ static bool isDeInterleaveMaskOfFactor(ArrayRef<int> Mask, unsigned Factor,
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/// <0, 2, 4, 6> (mask of index 0 to extract even elements)
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/// <1, 3, 5, 7> (mask of index 1 to extract odd elements)
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static bool isDeInterleaveMask(ArrayRef<int> Mask, unsigned &Factor,
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unsigned &Index, unsigned MaxFactor) {
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unsigned &Index, unsigned MaxFactor,
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unsigned NumLoadElements) {
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if (Mask.size() < 2)
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return false;
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// Check potential Factors.
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for (Factor = 2; Factor <= MaxFactor; Factor++)
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for (Factor = 2; Factor <= MaxFactor; Factor++) {
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// Make sure we don't produce a load wider than the input load.
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if (Mask.size() * Factor > NumLoadElements)
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return false;
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if (isDeInterleaveMaskOfFactor(Mask, Factor, Index))
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return true;
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}
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return false;
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}
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@ -302,9 +307,10 @@ bool InterleavedAccess::lowerInterleavedLoad(
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unsigned Factor, Index;
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unsigned NumLoadElements = LI->getType()->getVectorNumElements();
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// Check if the first shufflevector is DE-interleave shuffle.
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if (!isDeInterleaveMask(Shuffles[0]->getShuffleMask(), Factor, Index,
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MaxFactor))
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MaxFactor, NumLoadElements))
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return false;
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// Holds the corresponding index for each DE-interleave shuffle.
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@ -352,9 +352,9 @@ define void @store_undef_mask_factor4(<16 x i32>* %ptr, <4 x i32> %v0, <4 x i32>
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ret void
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}
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define void @load_address_space(<4 x i32> addrspace(1)* %ptr) {
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define void @load_address_space(<8 x i32> addrspace(1)* %ptr) {
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; NEON-LABEL: @load_address_space(
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; NEON-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> addrspace(1)* %ptr to i8 addrspace(1)*
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; NEON-NEXT: [[TMP1:%.*]] = bitcast <8 x i32> addrspace(1)* %ptr to i8 addrspace(1)*
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; NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p1i8(i8 addrspace(1)* [[TMP1]], i32 0)
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; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 2
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; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLDN]], 1
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@ -364,10 +364,10 @@ define void @load_address_space(<4 x i32> addrspace(1)* %ptr) {
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; NO_NEON-NOT: @llvm.arm.neon
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; NO_NEON: ret void
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;
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%interleaved.vec = load <4 x i32>, <4 x i32> addrspace(1)* %ptr
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%v0 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 3>
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%v1 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 1, i32 4>
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%v2 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <2 x i32> <i32 2, i32 5>
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%interleaved.vec = load <8 x i32>, <8 x i32> addrspace(1)* %ptr
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%v0 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <2 x i32> <i32 0, i32 3>
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%v1 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <2 x i32> <i32 1, i32 4>
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%v2 = shufflevector <8 x i32> %interleaved.vec, <8 x i32> undef, <2 x i32> <i32 2, i32 5>
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ret void
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}
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@ -883,3 +883,16 @@ define void @load_factor2_wide_pointer(<16 x i32*>* %ptr) {
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%v1 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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ret void
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}
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; This would be a candidate for interleaving, except that load doesn't
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; actually load enough elements to satisfy the shuffle masks. (It would be
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; possible to produce a vld2.v2i32, but that currently isn't implemented.)
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define void @load_out_of_range(<4 x i32>* %ptr) {
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; ALL-LABEL: @load_out_of_range(
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; ALL-NOT: @llvm.arm.neon
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; ALL: ret void
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%interleaved.vec = load <4 x i32>, <4 x i32>* %ptr, align 4
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%v0 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%v1 = shufflevector <4 x i32> %interleaved.vec, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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ret void
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}
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