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[Sparc] Add more instruction aliases.
These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
This commit is contained in:
James Y Knight
parent
91a40832bd
commit
528aaa5079
@ -245,6 +245,7 @@ multiclass fp_cond_alias<string cond, int condVal> {
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}
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defm : int_cond_alias<"a", 0b1000>;
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defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
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defm : int_cond_alias<"n", 0b0000>;
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defm : int_cond_alias<"ne", 0b1001>;
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defm : int_cond_alias<"nz", 0b1001>; // same as ne
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@ -266,6 +267,7 @@ defm : int_cond_alias<"vc", 0b1111>;
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defm : int_cond_alias<"vs", 0b0111>;
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defm : fp_cond_alias<"a", 0b0000>;
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defm : fp_cond_alias<"", 0b0000>; // same as a; gnu asm, not in manual
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defm : fp_cond_alias<"n", 0b1000>;
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defm : fp_cond_alias<"u", 0b0111>;
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defm : fp_cond_alias<"g", 0b0110>;
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@ -284,7 +286,16 @@ defm : fp_cond_alias<"le", 0b1101>;
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defm : fp_cond_alias<"ule", 0b1110>;
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defm : fp_cond_alias<"o", 0b1111>;
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// Instruction aliases for JMPL.
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// Section A.3 Synthetic Instructions
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// Most are marked as Emit=0, so that they are not used for disassembly. This is
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// an aesthetic issue, but the chosen policy is to typically prefer using the
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// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
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// call, tst, ret, retl.
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// Note: cmp is handled in SparcInstrInfo.
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// jmp/call/ret/retl have special case handling for output in
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// SparcInstPrinter.cpp
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// jmp addr -> jmpl addr, %g0
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def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
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@ -294,28 +305,129 @@ def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
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def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
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def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
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// retl -> RETL 8
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def : InstAlias<"retl", (RETL 8)>;
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// tst reg -> orcc %g0, reg, %g0
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def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
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// ret -> RET 8
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// ret -> jmpl %i7+8, %g0 (aka RET 8)
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def : InstAlias<"ret", (RET 8)>;
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// mov reg, rd -> or %g0, reg, rd
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def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
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// retl -> jmpl %o7+8, %g0 (aka RETL 8)
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def : InstAlias<"retl", (RETL 8)>;
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// mov simm13, rd -> or %g0, simm13, rd
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def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
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// restore -> restore %g0, %g0, %g0
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def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
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// flush -> flush %g0
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def : InstAlias<"flush", (FLUSH), 0>;
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// save -> restore %g0, %g0, %g0
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def : InstAlias<"save", (SAVErr G0, G0, G0)>;
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// set value, rd
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// (turns into a sequence of sethi+or, depending on the value)
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// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
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// restore -> restore %g0, %g0, %g0
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def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
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// not rd -> xnor rd, %g0, rd
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def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
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// not reg, rd -> xnor reg, %g0, rd
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def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
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// neg rd -> sub %g0, rd, rd
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def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
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// neg reg, rd -> sub %g0, reg, rd
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def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
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// inc rd -> add rd, 1, rd
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def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// inc simm13, rd -> add rd, simm13, rd
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def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// inccc rd -> addcc rd, 1, rd
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def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// inccc simm13, rd -> addcc rd, simm13, rd
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def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// dec rd -> sub rd, 1, rd
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def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// dec simm13, rd -> sub rd, simm13, rd
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def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// deccc rd -> subcc rd, 1, rd
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def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// deccc simm13, rd -> subcc rd, simm13, rd
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def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
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def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
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def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
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// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
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def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
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def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
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def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// clr rd -> or %g0, %g0, rd
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def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
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// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
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def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
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def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
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def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
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// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
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def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
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def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
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// mov specialreg, rd -> rd specialreg, rd
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def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
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def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
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def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
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def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
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// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
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def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
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// End of Section A.3
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// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
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// (aka: omit the first arg when it's g0. This is not in the manual, but is
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// supported by gnu and solaris as)
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def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
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// flush -> flush %g0
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def : InstAlias<"flush", (FLUSH), 0>;
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def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
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@ -536,6 +536,7 @@ let Defs = [ICC] in
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let Uses = [ICC] in
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defm SUBC : F3_12np <"subx", 0b001100>;
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// cmp (from Section A.3) is a specialized alias for subcc
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let Defs = [ICC], rd = 0 in {
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def CMPrr : F3_1<2, 0b010100,
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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@ -76,8 +76,8 @@
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! CHECK: mov 255, %g3 ! encoding: [0x86,0x10,0x20,0xff]
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mov 0xff, %g3
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! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00]
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restore %g0, %g0, %g0
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! CHECK: restore %g0, %g0, %g1 ! encoding: [0x83,0xe8,0x00,0x00]
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restore %g0, %g0, %g1
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! CHECK: addx %g2, %g1, %g3 ! encoding: [0x86,0x40,0x80,0x01]
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addx %g2, %g1, %g3
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@ -2,6 +2,26 @@
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! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
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! Section A.3 Synthetic Instructions
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! CHECK: cmp %g1, %g2 ! encoding: [0x80,0xa0,0x40,0x02]
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cmp %g1, %g2
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! CHECK: cmp %g1, 5 ! encoding: [0x80,0xa0,0x60,0x05]
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cmp %g1, 5
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! jmp and call are tested in sparc-ctrl-instructions.
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! CHECK: tst %g1 ! encoding: [0x80,0x90,0x40,0x00]
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tst %g1
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! CHECK: ret ! encoding: [0x81,0xc7,0xe0,0x08]
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ret
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! CHECK: retl ! encoding: [0x81,0xc3,0xe0,0x08]
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retl
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! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00]
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restore
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! CHECK: save ! encoding: [0x81,0xe0,0x00,0x00]
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save
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! CHECK: sethi %hi(40000), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
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! CHECK: ! fixup A - offset: 0, value: %hi(40000), kind: fixup_sparc_hi22
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! CHECK: or %g1, %lo(40000), %g1 ! encoding: [0x82,0x10,0b011000AA,A]
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@ -10,8 +30,116 @@
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! CHECK: mov %lo(1), %g1 ! encoding: [0x82,0x10,0b001000AA,A]
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! CHECK: ! fixup A - offset: 0, value: %lo(1), kind: fixup_sparc_lo10
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set 1, %g1
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! CHECK: sethi %hi(32768), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
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! CHECK: ! fixup A - offset: 0, value: %hi(32768), kind: fixup_sparc_hi22
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set 32768, %g1
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! CHECK: xnor %g1, %g0, %g2 ! encoding: [0x84,0x38,0x40,0x00]
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not %g1, %g2
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! CHECK: xnor %g1, %g0, %g1 ! encoding: [0x82,0x38,0x40,0x00]
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not %g1
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! CHECK: sub %g0, %g1, %g2 ! encoding: [0x84,0x20,0x00,0x01]
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neg %g1, %g2
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! CHECK: sub %g0, %g1, %g1 ! encoding: [0x82,0x20,0x00,0x01]
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neg %g1
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! CHECK: add %g1, 1, %g1 ! encoding: [0x82,0x00,0x60,0x01]
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inc %g1
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! CHECK: add %g1, 55, %g1 ! encoding: [0x82,0x00,0x60,0x37]
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inc 55, %g1
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! CHECK: addcc %g1, 1, %g1 ! encoding: [0x82,0x80,0x60,0x01]
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inccc %g1
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! CHECK: addcc %g1, 55, %g1 ! encoding: [0x82,0x80,0x60,0x37]
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inccc 55, %g1
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! CHECK: sub %g1, 1, %g1 ! encoding: [0x82,0x20,0x60,0x01]
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dec %g1
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! CHECK: sub %g1, 55, %g1 ! encoding: [0x82,0x20,0x60,0x37]
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dec 55, %g1
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! CHECK: subcc %g1, 1, %g1 ! encoding: [0x82,0xa0,0x60,0x01]
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deccc %g1
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! CHECK: subcc %g1, 55, %g1 ! encoding: [0x82,0xa0,0x60,0x37]
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deccc 55, %g1
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! CHECK: andcc %g2, %g1, %g0 ! encoding: [0x80,0x88,0x80,0x01]
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btst %g1, %g2
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! CHECK: andcc %g2, 4, %g0 ! encoding: [0x80,0x88,0xa0,0x04]
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btst 4, %g2
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! CHECK: or %g2, %g1, %g2 ! encoding: [0x84,0x10,0x80,0x01]
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bset %g1, %g2
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! CHECK: or %g2, 4, %g2 ! encoding: [0x84,0x10,0xa0,0x04]
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bset 4, %g2
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! CHECK: andn %g2, %g1, %g2 ! encoding: [0x84,0x28,0x80,0x01]
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bclr %g1, %g2
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! CHECK: andn %g2, 4, %g2 ! encoding: [0x84,0x28,0xa0,0x04]
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bclr 4, %g2
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! CHECK: xor %g2, %g1, %g2 ! encoding: [0x84,0x18,0x80,0x01]
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btog %g1, %g2
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! CHECK: xor %g2, 4, %g2 ! encoding: [0x84,0x18,0xa0,0x04]
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btog 4, %g2
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! CHECK: mov %g0, %g1 ! encoding: [0x82,0x10,0x00,0x00]
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clr %g1
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! CHECK: stb %g0, [%g1+%g2] ! encoding: [0xc0,0x28,0x40,0x02]
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clrb [%g1+%g2]
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! CHECK: sth %g0, [%g1+%g2] ! encoding: [0xc0,0x30,0x40,0x02]
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clrh [%g1+%g2]
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! CHECK: st %g0, [%g1+%g2] ! encoding: [0xc0,0x20,0x40,0x02]
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clr [%g1+%g2]
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! mov reg_or_imm,reg tested in sparc-alu-instructions.s
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! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
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mov %y, %i0
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! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00]
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mov %asr1, %i0
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! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00]
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mov %psr, %i0
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! CHECK: rd %wim, %i0 ! encoding: [0xb1,0x50,0x00,0x00]
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mov %wim, %i0
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! CHECK: rd %tbr, %i0 ! encoding: [0xb1,0x58,0x00,0x00]
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mov %tbr, %i0
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! CHECK: wr %g0, %i0, %y ! encoding: [0x81,0x80,0x00,0x18]
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mov %i0, %y
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! CHECK: wr %g0, 5, %y ! encoding: [0x81,0x80,0x20,0x05]
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mov 5, %y
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! CHECK: wr %g0, %i0, %asr15 ! encoding: [0x9f,0x80,0x00,0x18]
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mov %i0, %asr15
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! CHECK: wr %g0, 5, %asr15 ! encoding: [0x9f,0x80,0x20,0x05]
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mov 5, %asr15
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! CHECK: wr %g0, %i0, %psr ! encoding: [0x81,0x88,0x00,0x18]
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mov %i0, %psr
|
||||
! CHECK: wr %g0, 5, %psr ! encoding: [0x81,0x88,0x20,0x05]
|
||||
mov 5, %psr
|
||||
! CHECK: wr %g0, %i0, %wim ! encoding: [0x81,0x90,0x00,0x18]
|
||||
mov %i0, %wim
|
||||
! CHECK: wr %g0, 5, %wim ! encoding: [0x81,0x90,0x20,0x05]
|
||||
mov 5, %wim
|
||||
! CHECK: wr %g0, %i0, %tbr ! encoding: [0x81,0x98,0x00,0x18]
|
||||
mov %i0, %tbr
|
||||
! CHECK: wr %g0, 5, %tbr ! encoding: [0x81,0x98,0x20,0x05]
|
||||
mov 5, %tbr
|
||||
|
||||
! Other aliases
|
||||
! CHECK: wr %g0, %i0, %y ! encoding: [0x81,0x80,0x00,0x18]
|
||||
wr %i0, %y
|
||||
! CHECK: wr %g0, 5, %y ! encoding: [0x81,0x80,0x20,0x05]
|
||||
wr 5, %y
|
||||
! CHECK: wr %g0, %i0, %asr15 ! encoding: [0x9f,0x80,0x00,0x18]
|
||||
wr %i0, %asr15
|
||||
! CHECK: wr %g0, 5, %asr15 ! encoding: [0x9f,0x80,0x20,0x05]
|
||||
wr 5, %asr15
|
||||
! CHECK: wr %g0, %i0, %psr ! encoding: [0x81,0x88,0x00,0x18]
|
||||
wr %i0, %psr
|
||||
! CHECK: wr %g0, 5, %psr ! encoding: [0x81,0x88,0x20,0x05]
|
||||
wr 5, %psr
|
||||
! CHECK: wr %g0, %i0, %wim ! encoding: [0x81,0x90,0x00,0x18]
|
||||
wr %i0, %wim
|
||||
! CHECK: wr %g0, 5, %wim ! encoding: [0x81,0x90,0x20,0x05]
|
||||
wr 5, %wim
|
||||
! CHECK: wr %g0, %i0, %tbr ! encoding: [0x81,0x98,0x00,0x18]
|
||||
wr %i0, %tbr
|
||||
! CHECK: wr %g0, 5, %tbr ! encoding: [0x81,0x98,0x20,0x05]
|
||||
wr 5, %tbr
|
||||
|
||||
Loading…
Reference in New Issue
Block a user