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AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CI
Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11604 llvm-svn: 244254
This commit is contained in:
Tom Stellard
parent
5d9e608825
commit
544c5ba738
@ -113,8 +113,10 @@ private:
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bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
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bool &Imm) const;
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bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
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bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
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bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
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bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
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bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
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bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
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SDNode *SelectAddrSpaceCast(SDNode *N);
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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@ -1191,14 +1193,19 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
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return true;
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}
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if (isUInt<32>(ByteOffset)) {
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if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
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return false;
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if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
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// 32-bit Immediates are supported on Sea Islands.
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Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
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} else {
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SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
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Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
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C32Bit), 0);
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Imm = false;
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return true;
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}
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return false;
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Imm = false;
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
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@ -1226,10 +1233,24 @@ bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
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return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
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SDValue &Offset) const {
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if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
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return false;
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bool Imm;
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if (!SelectSMRD(Addr, SBase, Offset, Imm))
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return false;
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return !Imm && isa<ConstantSDNode>(Offset);
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm;
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return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
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!isa<ConstantSDNode>(Offset);
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
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@ -1238,10 +1259,23 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
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return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
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SDValue &Offset) const {
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if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
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return false;
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bool Imm;
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if (!SelectSMRDOffset(Addr, Offset, Imm))
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return false;
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return !Imm && isa<ConstantSDNode>(Offset);
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRDOffset(Addr, Offset, Imm) && !Imm;
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return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
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!isa<ConstantSDNode>(Offset);
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}
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// FIXME: This is incorrect and only enough to be able to compile.
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@ -301,6 +301,8 @@ public:
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bool isDSOffset01() const;
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bool isSWaitCnt() const;
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bool isMubufOffset() const;
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bool isSMRDOffset() const;
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bool isSMRDLiteralOffset() const;
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};
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class AMDGPUAsmParser : public MCTargetAsmParser {
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@ -1570,6 +1572,23 @@ AMDGPUAsmParser::parseR128(OperandVector &Operands) {
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return parseNamedBit("r128", Operands);
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}
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//===----------------------------------------------------------------------===//
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// smrd
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//===----------------------------------------------------------------------===//
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bool AMDGPUOperand::isSMRDOffset() const {
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// FIXME: Support 20-bit offsets on VI. We need to to pass subtarget
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// information here.
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return isImm() && isUInt<8>(getImm());
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}
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bool AMDGPUOperand::isSMRDLiteralOffset() const {
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// 32-bit literals are only supported on CI and we only want to use them
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// when the offset is > 8-bits.
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return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
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}
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//===----------------------------------------------------------------------===//
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// vop3
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//===----------------------------------------------------------------------===//
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@ -231,7 +231,8 @@ class SMRD_IMMe_ci <bits<5> op> : Enc64 {
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let Inst{8} = 0;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
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let Inst{26-22} = 0x18; //encoding
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let Inst{63-32} = offset;
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}
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@ -8,6 +8,9 @@
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//===----------------------------------------------------------------------===//
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def isCI : Predicate<"Subtarget->getGeneration() "
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">= AMDGPUSubtarget::SEA_ISLANDS">;
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def isCIOnly : Predicate<"Subtarget->getGeneration() =="
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"AMDGPUSubtarget::SEA_ISLANDS">,
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AssemblerPredicate <"FeatureSeaIslands">;
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def isVI : Predicate <
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"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
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AssemblerPredicate<"FeatureGCN3Encoding">;
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@ -436,6 +439,17 @@ def ClampMatchClass : AsmOperandClass {
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let RenderMethod = "addImmOperands";
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}
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class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
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let Name = "SMRDOffset"#predicate;
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let PredicateMethod = predicate;
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let RenderMethod = "addImmOperands";
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}
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def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
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def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
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"isSMRDLiteralOffset"
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>;
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let OperandType = "OPERAND_IMMEDIATE" in {
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def offen : Operand<i1> {
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@ -510,6 +524,16 @@ def ClampMod : Operand <i1> {
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let ParserMatchClass = ClampMatchClass;
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}
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def smrd_offset : Operand <i32> {
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let PrintMethod = "printU32ImmOperand";
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let ParserMatchClass = SMRDOffsetMatchClass;
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}
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def smrd_literal_offset : Operand <i32> {
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let PrintMethod = "printU32ImmOperand";
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let ParserMatchClass = SMRDLiteralOffsetMatchClass;
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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def VOPDstS64 : VOPDstOperand <SReg_64>;
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@ -529,11 +553,12 @@ def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
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def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
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def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
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def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
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def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
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def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
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def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
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def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
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def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
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@ -893,14 +918,14 @@ multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
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RegisterClass dstClass> {
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defm _IMM : SMRD_m <
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op, opName#"_IMM", 1, (outs dstClass:$dst),
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(ins baseClass:$sbase, u32imm:$offset),
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(ins baseClass:$sbase, smrd_offset:$offset),
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opName#" $dst, $sbase, $offset", []
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>;
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def _IMM_ci : SMRD <
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(outs dstClass:$dst), (ins baseClass:$sbase, u32imm:$offset),
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(outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
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opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op> {
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let AssemblerPredicates = [isCI];
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let AssemblerPredicates = [isCIOnly];
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}
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defm _SGPR : SMRD_m <
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@ -2072,27 +2072,34 @@ def : Pat <
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// SMRD Patterns
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//===----------------------------------------------------------------------===//
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multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
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multiclass SMRD_Pattern <string Instr, ValueType vt> {
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// 1. IMM offset
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def : Pat <
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(constant_load (SMRDImm i64:$sbase, i32:$offset)),
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(vt (Instr_IMM $sbase, $offset))
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(vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
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>;
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// 2. SGPR offset
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def : Pat <
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(constant_load (SMRDSgpr i64:$sbase, i32:$offset)),
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(vt (Instr_SGPR $sbase, $offset))
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(vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
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>;
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def : Pat <
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(constant_load (SMRDImm32 i64:$sbase, i32:$offset)),
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(vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
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> {
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let Predicates = [isCIOnly];
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}
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}
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defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX8", v32i8>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
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// 1. Offset as an immediate
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def : Pat <
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@ -2106,6 +2113,15 @@ def : Pat <
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
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>;
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let Predicates = [isCI] in {
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def : Pat <
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(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
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(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
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>;
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} // End Predicates = [isCI]
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//===----------------------------------------------------------------------===//
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// SOP1 Patterns
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//===----------------------------------------------------------------------===//
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@ -1,9 +1,10 @@
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; RUN: llc < %s -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
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; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=CI --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
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; SMRD load with an immediate offset.
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; GCN-LABEL: {{^}}smrd0:
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
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define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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@ -15,7 +16,7 @@ entry:
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; SMRD load with the largest possible immediate offset.
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; GCN-LABEL: {{^}}smrd1:
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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@ -29,6 +30,7 @@ entry:
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; GCN-LABEL: {{^}}smrd2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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; GCN: s_endpgm
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define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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@ -58,6 +60,7 @@ entry:
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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@ -69,9 +72,9 @@ entry:
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; GCN: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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@ -83,7 +86,7 @@ entry:
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; SMRD load using the load.const intrinsic with an immediate offset
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; GCN-LABEL: {{^}}smrd_load_const0:
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
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define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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@ -97,7 +100,7 @@ main_body:
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; SMRD load using the load.const intrinsic with the largest possible immediate
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; offset.
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; GCN-LABEL: {{^}}smrd_load_const1:
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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@ -113,6 +116,7 @@ main_body:
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; GCN-LABEL: {{^}}smrd_load_const2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
|
||||
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
|
||||
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
|
||||
define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
@ -127,6 +131,7 @@ main_body:
|
||||
; GCN-LABEL: {{^}}smrd_load_const3:
|
||||
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
|
||||
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
|
||||
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
|
||||
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
|
||||
define void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
@ -139,9 +144,9 @@ main_body:
|
||||
|
||||
; SMRD load with an offset greater than the largest possible immediate on VI
|
||||
; GCN-LABEL: {{^}}smrd_load_const4:
|
||||
; GCN: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
|
||||
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
|
||||
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
|
||||
; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
|
||||
; SIVI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
|
||||
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
|
||||
; GCN: s_endpgm
|
||||
define void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
|
||||
@ -1,32 +1,53 @@
|
||||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI %s
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
|
||||
|
||||
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Offset Handling
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
s_load_dword s1, s[2:3], 0xfc
|
||||
// GCN: s_load_dword s1, s[2:3], 0xfc ; encoding: [0xfc,0x83,0x00,0xc0]
|
||||
|
||||
s_load_dword s1, s[2:3], 0xff
|
||||
// GCN: s_load_dword s1, s[2:3], 0xff ; encoding: [0xff,0x83,0x00,0xc0]
|
||||
|
||||
s_load_dword s1, s[2:3], 0x100
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: s_load_dword s1, s[2:3], 0x100 ; encoding: [0xff,0x82,0x00,0xc0,0x00,0x01,0x00,0x00]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
s_load_dword s1, s[2:3], 1
|
||||
// CHECK: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
|
||||
// GCN: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
|
||||
|
||||
s_load_dword s1, s[2:3], s4
|
||||
// CHECK: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
|
||||
// GCN: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
|
||||
|
||||
s_load_dwordx2 s[2:3], s[2:3], 1
|
||||
// CHECK: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
|
||||
// GCN: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
|
||||
|
||||
s_load_dwordx2 s[2:3], s[2:3], s4
|
||||
// CHECK: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
|
||||
// GCN: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
|
||||
|
||||
s_load_dwordx4 s[4:7], s[2:3], 1
|
||||
// CHECK: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
|
||||
// GCN: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
|
||||
|
||||
s_load_dwordx4 s[4:7], s[2:3], s4
|
||||
// CHECK: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
|
||||
// GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
|
||||
|
||||
s_load_dwordx8 s[8:15], s[2:3], 1
|
||||
// CHECK: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
|
||||
// GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
|
||||
|
||||
s_load_dwordx8 s[8:15], s[2:3], s4
|
||||
// CHECK: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0]
|
||||
// GCN: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0]
|
||||
|
||||
s_load_dwordx16 s[16:31], s[2:3], 1
|
||||
// CHECK: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
|
||||
// GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
|
||||
|
||||
s_load_dwordx16 s[16:31], s[2:3], s4
|
||||
// CHECK: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1]
|
||||
// GCN: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user