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[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes
See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D36322 llvm-svn: 310497
This commit is contained in:
Dmitry Preobrazhensky
parent
5a8769dcd9
commit
559a664ace
@ -70,7 +70,8 @@ enum SIEncodingFamily {
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SI = 0,
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VI = 1,
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SDWA = 2,
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SDWA9 = 3
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SDWA9 = 3,
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GFX9 = 4
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};
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// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
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@ -110,6 +111,10 @@ int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
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Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9
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: SIEncodingFamily::SDWA;
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if ((get(Opcode).TSFlags & SIInstrFlags::F16_ZFILL) != 0 &&
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ST.getGeneration() >= AMDGPUSubtarget::GFX9)
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Gen = SIEncodingFamily::GFX9;
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int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
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// -1 means that Opcode is already a native instruction.
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@ -208,6 +208,9 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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if (Res) break;
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Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
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if (Res) break;
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Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
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} while (false);
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if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
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@ -69,7 +69,8 @@ enum : uint64_t {
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VOPAsmPrefer32Bit = UINT64_C(1) << 41,
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HasFPClamp = UINT64_C(1) << 42,
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VOP3_OPSEL = UINT64_C(1) << 43,
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maybeAtomic = UINT64_C(1) << 44
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maybeAtomic = UINT64_C(1) << 44,
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F16_ZFILL = UINT64_C(1) << 45
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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@ -90,6 +90,10 @@ class InstSI <dag outs, dag ins, string asm = "",
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// Is it possible for this instruction to be atomic?
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field bit maybeAtomic = 0;
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// This bit indicates that this is a 16-bit instruction which zero-fills
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// unused bits in dst. Note that new GFX9 opcodes preserve unused bits.
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field bit F16_ZFILL = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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@ -137,6 +141,7 @@ class InstSI <dag outs, dag ins, string asm = "",
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let TSFlags{43} = VOP3_OPSEL;
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let TSFlags{44} = maybeAtomic;
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let TSFlags{45} = F16_ZFILL;
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let SchedRW = [Write32Bit];
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@ -11,6 +11,9 @@ def isCI : Predicate<"Subtarget->getGeneration() "
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def isCIOnly : Predicate<"Subtarget->getGeneration() =="
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"SISubtarget::SEA_ISLANDS">,
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AssemblerPredicate <"FeatureSeaIslands">;
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def isVIOnly : Predicate<"Subtarget->getGeneration() =="
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"SISubtarget::VOLCANIC_ISLANDS">,
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AssemblerPredicate <"FeatureVolcanicIslands">;
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def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
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@ -22,6 +25,7 @@ def SIEncodingFamily {
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int VI = 1;
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int SDWA = 2;
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int SDWA9 = 3;
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int GFX9 = 4;
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}
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//===----------------------------------------------------------------------===//
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@ -1762,7 +1766,8 @@ def getMCOpcodeGen : InstrMapping {
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let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
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[!cast<string>(SIEncodingFamily.VI)],
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[!cast<string>(SIEncodingFamily.SDWA)],
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[!cast<string>(SIEncodingFamily.SDWA9)]];
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[!cast<string>(SIEncodingFamily.SDWA9)],
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[!cast<string>(SIEncodingFamily.GFX9)]];
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}
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// Get equivalent SOPK instruction.
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@ -372,21 +372,33 @@ def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
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let SubtargetPredicate = Has16BitInsts in {
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def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
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let F16_ZFILL = 1 in {
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def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
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}
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let SubtargetPredicate = isGFX9 in {
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def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
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}
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let isCommutable = 1 in {
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def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
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let F16_ZFILL = 1 in {
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def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
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def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
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}
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let SubtargetPredicate = isGFX9 in {
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def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
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def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
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} // End SubtargetPredicate = isGFX9
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def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
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def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
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def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
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def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
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def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
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} // End isCommutable = 1
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} // End SubtargetPredicate = Has16BitInsts
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@ -587,6 +599,27 @@ multiclass VOP3Interp_Real_vi<bits<10> op> {
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} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
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let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
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multiclass VOP3_F16_Real_vi<bits<10> op> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
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VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
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}
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} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
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let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
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multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
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VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
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VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
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let AsmString = AsmName # ps.AsmOperands;
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}
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}
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} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
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defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
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defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
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@ -631,14 +664,25 @@ defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
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defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
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defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
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defm V_MAD_F16 : VOP3_Real_vi <0x1ea>;
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defm V_MAD_U16 : VOP3_Real_vi <0x1eb>;
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defm V_MAD_I16 : VOP3_Real_vi <0x1ec>;
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defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
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defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
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defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
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defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
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defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
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defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
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defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
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defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
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defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
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defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
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defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
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defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
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defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
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defm V_MAD_F16_gfx9 : VOP3_F16_Real_gfx9 <0x203, "V_MAD_F16_gfx9", "v_mad_f16">;
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defm V_MAD_U16_gfx9 : VOP3_F16_Real_gfx9 <0x204, "V_MAD_U16_gfx9", "v_mad_u16">;
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defm V_MAD_I16_gfx9 : VOP3_F16_Real_gfx9 <0x205, "V_MAD_I16_gfx9", "v_mad_i16">;
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defm V_FMA_F16_gfx9 : VOP3_F16_Real_gfx9 <0x206, "V_FMA_F16_gfx9", "v_fma_f16">;
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defm V_DIV_FIXUP_F16_gfx9 : VOP3_F16_Real_gfx9 <0x207, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
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defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
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defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
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@ -190,3 +190,135 @@ v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
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v_sub_i16 v5, v1, v2 clamp
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// GFX9: v_sub_i16 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
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v_fma_f16_e64 v5, v1, v2, v3
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// GFX9: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, -v2, v3
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// GFX9: v_fma_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
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v_fma_f16 v5, v1, v2, |v3|
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// GFX9: v_fma_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, v2, v3 clamp
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// GFX9: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_legacy_f16_e64 v5, v1, v2, v3
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// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_fma_legacy_f16 v5, -v1, v2, v3
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// GFX9: v_fma_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
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v_fma_legacy_f16 v5, v1, |v2|, v3
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// GFX9: v_fma_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_fma_legacy_f16 v5, v1, v2, v3 clamp
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// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_div_fixup_f16_e64 v5, 0.5, v2, v3
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// GFX9: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
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v_div_fixup_f16 v5, v1, 0.5, v3
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// GFX9: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
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v_div_fixup_f16 v5, v1, v2, 0.5
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// GFX9: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
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v_div_fixup_f16 v5, -v1, v2, v3
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// GFX9: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
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v_div_fixup_f16 v5, |v1|, v2, v3
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// GFX9: v_div_fixup_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
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v_div_fixup_f16 v5, v1, v2, v3 clamp
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// GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
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v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3
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// GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
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v_div_fixup_legacy_f16 v5, v1, 0.5, v3
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// GFX9: v_div_fixup_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
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v_div_fixup_legacy_f16 v5, v1, v2, 0.5
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// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
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v_div_fixup_legacy_f16 v5, -v1, v2, v3
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// GFX9: v_div_fixup_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
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v_div_fixup_legacy_f16 v5, v1, |v2|, v3
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// GFX9: v_div_fixup_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
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v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
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// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_f16_e64 v5, 0.5, v2, v3
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// GFX9: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
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v_mad_f16 v5, v1, 0.5, v3
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// GFX9: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
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v_mad_f16 v5, v1, v2, 0.5
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// GFX9: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
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v_mad_f16 v5, v1, v2, -v3
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// GFX9: v_mad_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
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v_mad_f16 v5, v1, v2, |v3|
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// GFX9: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
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v_mad_f16 v5, v1, v2, v3 clamp
|
||||
// GFX9: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_i16_e64 v5, 0, v2, v3
|
||||
// GFX9: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_i16 v5, v1, -1, v3
|
||||
// GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
|
||||
|
||||
v_mad_i16 v5, v1, v2, -4.0
|
||||
// GFX9: v_mad_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
|
||||
|
||||
v_mad_legacy_f16_e64 v5, 0.5, v2, v3
|
||||
// GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_legacy_f16 v5, v1, 0.5, v3
|
||||
// GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
|
||||
v_mad_legacy_f16 v5, v1, v2, 0.5
|
||||
// GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
|
||||
|
||||
v_mad_legacy_f16 v5, v1, -v2, v3
|
||||
// GFX9: v_mad_legacy_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
|
||||
|
||||
v_mad_legacy_f16 v5, v1, |v2|, v3
|
||||
// GFX9: v_mad_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_legacy_f16 v5, v1, v2, v3 clamp
|
||||
// GFX9: v_mad_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_legacy_i16_e64 v5, 0, v2, v3
|
||||
// GFX9: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_legacy_i16 v5, v1, -1, v3
|
||||
// GFX9: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
|
||||
|
||||
v_mad_legacy_i16 v5, v1, v2, -4.0
|
||||
// GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
|
||||
|
||||
v_mad_legacy_u16_e64 v5, 0, v2, v3
|
||||
// GFX9: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_legacy_u16 v5, v1, -1, v3
|
||||
// GFX9: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
|
||||
|
||||
v_mad_legacy_u16 v5, v1, v2, -4.0
|
||||
// GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
|
||||
|
||||
v_mad_u16_e64 v5, 0, v2, v3
|
||||
// GFX9: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_u16 v5, v1, -1, v3
|
||||
// GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
|
||||
|
||||
v_mad_u16 v5, v1, v2, -4.0
|
||||
// GFX9: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
|
||||
|
||||
@ -436,6 +436,88 @@ v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
|
||||
// SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
|
||||
// VI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
|
||||
|
||||
///===---------------------------------------------------------------------===//
|
||||
// VOP3 Legacy
|
||||
///===---------------------------------------------------------------------===//
|
||||
|
||||
v_fma_f16_e64 v5, v1, v2, v3
|
||||
// VI: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_fma_f16 v5, v1, v2, 0.5
|
||||
// VI: v_fma_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
|
||||
|
||||
v_fma_f16 v5, -v1, -v2, -v3
|
||||
// VI: v_fma_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
|
||||
|
||||
v_fma_f16 v5, |v1|, |v2|, |v3|
|
||||
// VI: v_fma_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_fma_f16 v5, v1, v2, v3 clamp
|
||||
// VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_div_fixup_f16_e64 v5, v1, v2, v3
|
||||
// VI: v_div_fixup_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_div_fixup_f16 v5, 0.5, v2, v3
|
||||
// VI: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
|
||||
v_div_fixup_f16 v5, v1, 0.5, v3
|
||||
// VI: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
|
||||
v_div_fixup_f16 v5, v1, v2, 0.5
|
||||
// VI: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
|
||||
|
||||
v_div_fixup_f16 v5, v1, v2, -4.0
|
||||
// VI: v_div_fixup_f16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
|
||||
|
||||
v_div_fixup_f16 v5, -v1, v2, v3
|
||||
// VI: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
|
||||
|
||||
v_div_fixup_f16 v5, v1, |v2|, v3
|
||||
// VI: v_div_fixup_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_div_fixup_f16 v5, v1, v2, v3 clamp
|
||||
// VI: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_f16_e64 v5, v1, v2, v3
|
||||
// VI: v_mad_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_f16 v5, 0.5, v2, v3
|
||||
// VI: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_f16 v5, v1, 0.5, v3
|
||||
// VI: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
|
||||
v_mad_f16 v5, v1, v2, 0.5
|
||||
// VI: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
|
||||
|
||||
v_mad_f16 v5, v1, -v2, v3
|
||||
// VI: v_mad_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
|
||||
|
||||
v_mad_f16 v5, v1, v2, |v3|
|
||||
// VI: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_f16 v5, v1, v2, v3 clamp
|
||||
// VI: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_i16_e64 v5, -1, v2, v3
|
||||
// VI: v_mad_i16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_i16 v5, v1, -4.0, v3
|
||||
// VI: v_mad_i16 v5, v1, -4.0, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
|
||||
|
||||
v_mad_i16 v5, v1, v2, 0
|
||||
// VI: v_mad_i16 v5, v1, v2, 0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
|
||||
|
||||
v_mad_u16_e64 v5, -1, v2, v3
|
||||
// VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
|
||||
|
||||
v_mad_u16 v5, v1, 0, v3
|
||||
// VI: v_mad_u16 v5, v1, 0, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
|
||||
|
||||
v_mad_u16 v5, v1, v2, -4.0
|
||||
// VI: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
|
||||
|
||||
//
|
||||
// v_interp*
|
||||
//
|
||||
|
||||
133
test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Normal file
133
test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Normal file
@ -0,0 +1,133 @@
|
||||
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx901 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
|
||||
|
||||
# GFX9: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_fma_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
|
||||
0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24
|
||||
|
||||
# GFX9: v_fma_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# GFX9: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_fma_legacy_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
|
||||
0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84
|
||||
|
||||
# CHECK: v_fma_legacy_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_fma_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
|
||||
0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
|
||||
0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
|
||||
0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
|
||||
0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03
|
||||
|
||||
# CHECK: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
|
||||
0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_legacy_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
|
||||
0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
|
||||
|
||||
# CHECK: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
|
||||
0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
|
||||
0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
|
||||
0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03
|
||||
@ -240,6 +240,72 @@
|
||||
# VI: v_ceil_f32_e64 v0, neg(-1.0) ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
|
||||
0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
|
||||
|
||||
# VI: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# VI: v_fma_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# VI: v_fma_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
|
||||
0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
|
||||
|
||||
# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
||||
0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04]
|
||||
0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_i16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03]
|
||||
0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03
|
||||
|
||||
# CHECK: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
|
||||
0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
|
||||
|
||||
# CHECK: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
|
||||
0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
|
||||
|
||||
# CHECK: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
|
||||
0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
|
||||
|
||||
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
|
||||
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user