RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-05 18:49:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[X86] Remove LowerVSETCC code for handling vXi1 setcc with vXi8/vXi16 input type. NFC

Browse Source 
These kinds of setccs are promoted by a DAG combine before they ever get to legalization.

llvm-svn: 323501
This commit is contained in:
Craig Topper 2018-01-26 07:15:17 +00:00
parent f85eadaa6c
commit 55f9d42328
1 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -17944,12 +17944,9 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
if (VT.getVectorElementType() == MVT::i1) {
// In AVX-512 architecture setcc returns mask with i1 elements,
// But there is no compare instruction for i8 and i16 elements in KNL.
// In this case use SSE compare
if (OpVT.getScalarSizeInBits() >= 32 || Subtarget.hasBWI())
return LowerIntVSETCC_AVX512(Op, DAG);
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
assert((OpVT.getScalarSizeInBits() >= 32 || Subtarget.hasBWI()) &&
"Unexpected operand type");
return LowerIntVSETCC_AVX512(Op, DAG);
}
// Lower using XOP integer comparisons.