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Add support for additional reduction variables: AND, OR, XOR.
Patch by Paul Redmond <paul.redmond@intel.com>. llvm-svn: 166649
This commit is contained in:
Nadav Rotem
parent
2c52fa4715
commit
5635a9350f
@ -208,7 +208,10 @@ public:
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enum ReductionKind {
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NoReduction = -1, /// Not a reduction.
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IntegerAdd = 0, /// Sum of numbers.
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IntegerMult = 1 /// Product of numbers.
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IntegerMult = 1, /// Product of numbers.
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IntegerOr = 2, /// Bitwise or logical OR of numbers.
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IntegerAnd = 3, /// Bitwise or logical AND of numbers.
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IntegerXor = 4 /// Bitwise or logical XOR of numbers.
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};
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/// This POD struct holds information about reduction variables.
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@ -981,14 +984,28 @@ SingleBlockLoopVectorizer::vectorizeLoop(LoopVectorizationLegality *Legal) {
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// Extract the first scalar.
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Value *Scalar0 =
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Builder.CreateExtractElement(NewPhi, Builder.getInt32(0));
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// Extract and sum the remaining vector elements.
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// Extract and reduce the remaining vector elements.
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for (unsigned i=1; i < VF; ++i) {
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Value *Scalar1 =
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Builder.CreateExtractElement(NewPhi, Builder.getInt32(i));
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if (RdxDesc.Kind == LoopVectorizationLegality::IntegerAdd) {
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Scalar0 = Builder.CreateAdd(Scalar0, Scalar1);
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} else {
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Scalar0 = Builder.CreateMul(Scalar0, Scalar1);
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switch (RdxDesc.Kind) {
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case LoopVectorizationLegality::IntegerAdd:
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Scalar0 = Builder.CreateAdd(Scalar0, Scalar1);
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break;
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case LoopVectorizationLegality::IntegerMult:
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Scalar0 = Builder.CreateMul(Scalar0, Scalar1);
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break;
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case LoopVectorizationLegality::IntegerOr:
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Scalar0 = Builder.CreateOr(Scalar0, Scalar1);
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break;
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case LoopVectorizationLegality::IntegerAnd:
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Scalar0 = Builder.CreateAnd(Scalar0, Scalar1);
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break;
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case LoopVectorizationLegality::IntegerXor:
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Scalar0 = Builder.CreateXor(Scalar0, Scalar1);
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break;
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default:
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llvm_unreachable("Unknown reduction operation");
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}
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}
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@ -1099,7 +1116,19 @@ bool LoopVectorizationLegality::canVectorizeBlock(BasicBlock &BB) {
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continue;
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}
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if (AddReductionVar(Phi, IntegerMult)) {
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DEBUG(dbgs() << "LV: Found an Mult reduction PHI."<< *Phi <<"\n");
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DEBUG(dbgs() << "LV: Found a MUL reduction PHI."<< *Phi <<"\n");
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continue;
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}
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if (AddReductionVar(Phi, IntegerOr)) {
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DEBUG(dbgs() << "LV: Found an OR reduction PHI."<< *Phi <<"\n");
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continue;
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}
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if (AddReductionVar(Phi, IntegerAnd)) {
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DEBUG(dbgs() << "LV: Found an AND reduction PHI."<< *Phi <<"\n");
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continue;
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}
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if (AddReductionVar(Phi, IntegerXor)) {
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DEBUG(dbgs() << "LV: Found a XOR reduction PHI."<< *Phi <<"\n");
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continue;
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}
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@ -1373,6 +1402,12 @@ LoopVectorizationLegality::isReductionInstr(Instruction *I,
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case Instruction::UDiv:
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case Instruction::SDiv:
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return Kind == IntegerMult;
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case Instruction::And:
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return Kind == IntegerAnd;
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case Instruction::Or:
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return Kind == IntegerOr;
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case Instruction::Xor:
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return Kind == IntegerXor;
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}
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}
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@ -149,4 +149,83 @@ for.end: ; preds = %for.body, %entry
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ret i32 %sum.0.lcssa
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}
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;CHECK: @reduction_and
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;CHECK: and <4 x i32>
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;CHECK: ret i32
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define i32 @reduction_and(i32 %n, i32* nocapture %A, i32* nocapture %B) nounwind uwtable readonly {
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entry:
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%cmp7 = icmp sgt i32 %n, 0
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br i1 %cmp7, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %and, %for.body ], [ -1, %entry ]
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%arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
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%0 = load i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
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%1 = load i32* %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%and = and i32 %add, %result.08
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ -1, %entry ], [ %and, %for.body ]
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ret i32 %result.0.lcssa
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}
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;CHECK: @reduction_or
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;CHECK: or <4 x i32>
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;CHECK: ret i32
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define i32 @reduction_or(i32 %n, i32* nocapture %A, i32* nocapture %B) nounwind uwtable readonly {
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entry:
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%cmp7 = icmp sgt i32 %n, 0
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br i1 %cmp7, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %or, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
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%0 = load i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
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%1 = load i32* %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%or = or i32 %add, %result.08
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ 0, %entry ], [ %or, %for.body ]
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ret i32 %result.0.lcssa
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}
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;CHECK: @reduction_xor
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;CHECK: xor <4 x i32>
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;CHECK: ret i32
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define i32 @reduction_xor(i32 %n, i32* nocapture %A, i32* nocapture %B) nounwind uwtable readonly {
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entry:
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%cmp7 = icmp sgt i32 %n, 0
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br i1 %cmp7, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%result.08 = phi i32 [ %xor, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
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%0 = load i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
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%1 = load i32* %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%xor = xor i32 %add, %result.08
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%result.0.lcssa = phi i32 [ 0, %entry ], [ %xor, %for.body ]
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ret i32 %result.0.lcssa
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}
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