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[mips][mt][5/7] Add support for fork and yield instructions.

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Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35252

llvm-svn: 307808
This commit is contained in:
Simon Dardis 2017-07-12 16:23:57 +00:00
parent 364b080e0a
commit 579b27fc8f
7 changed files with 74 additions and 3 deletions
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27
lib/Target/Mips/MipsMTInstrFormats.td
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@ -49,3 +49,30 @@ class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
let Inst{4-3} = 0b00;
let Inst{2-0} = 0b001;
}
class SPECIAL3_MT_FORK : MipsMTInst {
bits<32> Inst;
bits<5> rs;
bits<5> rt;
bits<5> rd;
let Inst{31-26} = 0b011111; // SPECIAL3
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-11} = rd;
let Inst{10-6} = 0b00000;
let Inst{5-0} = 0b001000; // FORK
}
class SPECIAL3_MT_YIELD : MipsMTInst {
bits<32> Inst;
bits<5> rs;
bits<5> rd;
let Inst{31-26} = 0b011111; // SPECIAL3
let Inst{25-21} = rs;
let Inst{20-16} = 0b00000;
let Inst{15-11} = rd;
let Inst{10-6} = 0b00000;
let Inst{5-0} = 0b001001; // FORK
}

26
lib/Target/Mips/MipsMTInstrInfo.td
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@ -23,6 +23,10 @@ class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
OPCODE_SC_E>;
class FORK_ENC : SPECIAL3_MT_FORK;
class YIELD_ENC : SPECIAL3_MT_YIELD;
//===----------------------------------------------------------------------===//
// MIPS MT Instruction Descriptions
//===----------------------------------------------------------------------===//
@ -35,6 +39,22 @@ class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
InstrItinClass Itinerary = Itin;
}
class FORK_DESC {
dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
dag InOperandList = (ins GPR32Opnd:$rt);
string AsmString = "fork\t$rd, $rs, $rt";
list<dag> Pattern = [];
InstrItinClass Itinerary = II_FORK;
}
class YIELD_DESC {
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = "yield\t$rd, $rs";
list<dag> Pattern = [];
InstrItinClass Itinerary = II_YIELD;
}
class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
@ -55,6 +75,10 @@ let hasSideEffects = 1, isNotDuplicable = 1,
def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
def FORK : FORK_ENC, FORK_DESC, ASE_MT;
def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
}
//===----------------------------------------------------------------------===//
@ -69,4 +93,6 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
}

6
lib/Target/Mips/MipsSchedule.td
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@ -119,6 +119,7 @@ def II_EMT : InstrItinClass;
def II_EVPE : InstrItinClass;
def II_EXT : InstrItinClass; // Any EXT instruction
def II_FLOOR : InstrItinClass;
def II_FORK : InstrItinClass;
def II_INS : InstrItinClass; // Any INS instruction
def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
def II_J : InstrItinClass;
@ -349,6 +350,7 @@ def II_WRPGPR : InstrItinClass;
def II_RDPGPR : InstrItinClass;
def II_DVP : InstrItinClass;
def II_EVP : InstrItinClass;
def II_YIELD : InstrItinClass;
//===----------------------------------------------------------------------===//
// Mips Generic instruction itineraries.
@ -413,6 +415,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_EMT , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EVPE , [InstrStage<2, [ALU]>]>,
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_FORK , [InstrStage<1, [ALU]>]>,
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
InstrItinData<II_MOVE , [InstrStage<1, [ALU]>]>,
@ -678,5 +681,6 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_WRPGPR , [InstrStage<1, [ALU]>]>,
InstrItinData<II_RDPGPR , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DVP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_EVP , [InstrStage<1, [ALU]>]>
InstrItinData<II_EVP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_YIELD , [InstrStage<5, [ALU]>]>
]>;

8
lib/Target/Mips/MipsScheduleGeneric.td
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@ -187,7 +187,11 @@ def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; }
def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; }
def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; }
def GnereicReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>;
def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>;
def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> {
let Latency = 5;
}
def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>;
def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>;
def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>;
@ -266,6 +270,8 @@ def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>;
def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>;
def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>;
// MIPS32R6 and MIPS16e
// ====================

3
test/MC/Disassembler/Mips/mt/valid-r2-el.txt
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@ -7,4 +7,7 @@
0x01 0x00 0x66 0x41 # CHECK: dvpe $6
0x21 0x00 0x60 0x41 # CHECK: evpe
0x21 0x00 0x64 0x41 # CHECK: evpe $4
0x08 0x10 0x65 0x7c # CHECK: fork $2, $3, $5
0x09 0x00 0x80 0x7c # CHECK: yield $4
0x09 0x20 0xa0 0x7c # CHECK: yield $4, $5

3
test/MC/Disassembler/Mips/mt/valid-r2.txt
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@ -7,4 +7,7 @@
0x41 0x66 0x00 0x01 # CHECK: dvpe $6
0x41 0x60 0x00 0x21 # CHECK: evpe
0x41 0x64 0x00 0x21 # CHECK: evpe $4
0x7c 0x65 0x10 0x08 # CHECK: fork $2, $3, $5
0x7c 0x80 0x00 0x09 # CHECK: yield $4
0x7c 0xa0 0x20 0x09 # CHECK: yield $4, $5

4
test/MC/Mips/mt/valid.s
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@ -8,4 +8,6 @@
dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]
fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]
yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]