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Make CALL node consistent with RET node. Signness of value has type MVT::i32
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type for most (if not all) platforms while MVT::i1 is not. llvm-svn: 28511
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@ -2515,7 +2515,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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default: assert(0 && "Unknown type action!");
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case Legal:
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Ops.push_back(Op);
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Ops.push_back(DAG.getConstant(isSigned, MVT::i1));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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break;
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case Promote:
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if (MVT::isInteger(VT)) {
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@ -2526,7 +2526,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
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}
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Ops.push_back(Op);
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Ops.push_back(DAG.getConstant(isSigned, MVT::i1));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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break;
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case Expand:
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if (VT != MVT::Vector) {
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@ -2544,9 +2544,9 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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std::swap(Lo, Hi);
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Ops.push_back(Lo);
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Ops.push_back(DAG.getConstant(isSigned, MVT::i1));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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Ops.push_back(Hi);
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Ops.push_back(DAG.getConstant(isSigned, MVT::i1));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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} else {
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// Value scalarized into many values. Unimp for now.
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assert(0 && "Cannot expand i64 -> i16 yet!");
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@ -2565,7 +2565,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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// Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
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Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
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Ops.push_back(Op);
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Ops.push_back(DAG.getConstant(isSigned, MVT::i1));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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} else {
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assert(0 && "Don't support illegal by-val vector call args yet!");
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abort();
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