RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-30 08:44:48 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Extensive additions for supporting instruction scheduling.

Browse Source 
llvm-svn: 398
This commit is contained in:
Vikram S. Adve 2001-08-28 23:10:41 +00:00
parent f9fa4cc579
commit 5947c43319
2 changed files with 1252 additions and 175 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1352
include/llvm/CodeGen/Sparc.h
View File

File diff suppressed because it is too large Load Diff

75
lib/CodeGen/TargetMachine/Sparc/Sparc.cpp
View File

@ -14,6 +14,70 @@
//************************ Class Implementations **************************/
//---------------------------------------------------------------------------
// class UltraSparcInstrInfo
//
// Purpose:
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class MachineInstrInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcInstrInfo::UltraSparcInstrInfo()
: MachineInstrInfo(SparcMachineInstrDesc,
/*descSize = */ NUM_TOTAL_OPCODES,
/*numRealOpCodes = */ NUM_REAL_OPCODES)
{
}
//---------------------------------------------------------------------------
// class UltraSparcSchedInfo
//
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
// class MachineSchedInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
: MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
mii,
SparcRUsageDesc,
SparcInstrUsageDeltas,
SparcInstrIssueDeltas,
sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
longestIssueConflict = 0; // computed from issuesGaps[]
branchMispredictPenalty = 4; // 4 for SPARC IIi
branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
l1ICacheMissPenalty = 8; // ? for SPARC IIi
inOrderLoads = true; // true for SPARC IIi
inOrderIssue = true; // true for SPARC IIi
inOrderExec = false; // false for most architectures
inOrderRetire= true; // true for most architectures
// must be called after above parameters are initialized.
this->initializeResources();
}
void
UltraSparcSchedInfo::initializeResources()
{
// Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
MachineSchedInfo::initializeResources();
// Machine-dependent fixups go here. None for now.
}
//---------------------------------------------------------------------------
// class UltraSparcMachine
@ -27,14 +91,21 @@
//---------------------------------------------------------------------------
UltraSparc::UltraSparc()
: TargetMachine("UltraSparc-Native", new UltraSparcInstrInfo()) {
: TargetMachine("UltraSparc-Native")
{
machineInstrInfo = new UltraSparcInstrInfo;
machineSchedInfo = new UltraSparcSchedInfo(machineInstrInfo);
optSizeForSubWordData = 4;
minMemOpWordSize = 8;
maxAtomicMemOpWordSize = 8;
zeroRegNum = 0; // %g0 always gives 0 on Sparc
}
UltraSparc::~UltraSparc() {
UltraSparc::~UltraSparc()
{
delete (UltraSparcInstrInfo*) machineInstrInfo;
delete (UltraSparcSchedInfo*) machineSchedInfo;
}
//**************************************************************************/