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AArch64: only try to use scaled fcvt ops on legal vector types.

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Before we ended up calling getSimpleVectorType on a <3 x float>, which
asserted.

llvm-svn: 263169
This commit is contained in:
Tim Northover 2016-03-10 23:02:21 +00:00
parent 4aba3720bc
commit 594e5f0364
2 changed files with 10 additions and 1 deletions
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3
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -7687,7 +7687,8 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
SDValue Op = N->getOperand(0);
if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
Op.getOpcode() != ISD::FMUL)
return SDValue();
SDValue ConstVec = Op->getOperand(1);

8
test/CodeGen/AArch64/fcvt_combine.ll
View File

@ -152,3 +152,11 @@ define <2 x i32> @test14(<2 x float> %f) {
%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
ret <2 x i32> %vcvt.i
}
; CHECK-LABEL: test_illegal_fp_to_int:
; CHECK: fcvtzs.4s v0, v0, #2
define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
%val = fptosi <3 x float> %scale to <3 x i32>
ret <3 x i32> %val
}