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ARM: fix thumb1 nop decoding

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In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

llvm-svn: 184703
This commit is contained in:
Amaury de la Vieuville 2013-06-24 09:11:53 +00:00
parent 6eecd3f2cb
commit 5a373a526e
4 changed files with 4 additions and 19 deletions
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9
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -243,15 +243,6 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return;
}
// Thumb1 NOP
if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
printAnnotation(O, Annot);
return;
}
// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
// a single GPRPair reg operand is used in the .td file to replace the two

2
test/MC/ARM/thumb-nop.s
View File

@ -5,5 +5,5 @@
nop
@ CHECK-V6: nop @ encoding: [0xc0,0x46]
@ CHECK-V6: mov r8, r8 @ encoding: [0xc0,0x46]
@ CHECK-V7: nop @ encoding: [0x00,0xbf]

2
test/MC/ARM/thumb.s
View File

@ -42,7 +42,7 @@
@ CHECK: bkpt #2 @ encoding: [0x02,0xbe]
nop
@ CHECK: nop @ encoding: [0xc0,0x46]
@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]
cpsie aif
@ CHECK: cpsie aif @ encoding: [0x67,0xb6]

10
test/MC/Disassembler/ARM/thumb1.txt
View File

@ -279,9 +279,11 @@
#------------------------------------------------------------------------------
# CHECK: mov r3, r4
# CHECK: movs r1, r3
# CHECK: mov r8, r8
0x23 0x46
0x19 0x00
0xc0 0x46
#------------------------------------------------------------------------------
@ -309,14 +311,6 @@
0x63 0x42
#------------------------------------------------------------------------------
# NOP
#------------------------------------------------------------------------------
# CHECK: nop
0xc0 0x46
#------------------------------------------------------------------------------
# ORR
#------------------------------------------------------------------------------