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Add memory operand folding support for the SETcc family of

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instructions.

llvm-svn: 11907
This commit is contained in:
Alkis Evlogimenos 2004-02-27 16:13:37 +00:00
parent 5193c08a8a
commit 5ac109957f
2 changed files with 25 additions and 0 deletions
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13
lib/Target/X86/X86InstrInfo.td
View File

@ -506,18 +506,31 @@ def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [
// Condition code ops, incl. set if equal/not equal/...
def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
def SETBr : X86Inst<"setb" , 0x92, MRMS0r, Arg8>, TB; // R8 = < unsign
def SETBm : X86Inst<"setb" , 0x92, MRMS0m, Arg8>, TB; // [mem8] = < unsign
def SETAEr : X86Inst<"setae", 0x93, MRMS0r, Arg8>, TB; // R8 = >= unsign
def SETAEm : X86Inst<"setae", 0x93, MRMS0m, Arg8>, TB; // [mem8] = >= unsign
def SETEr : X86Inst<"sete" , 0x94, MRMS0r, Arg8>, TB; // R8 = ==
def SETEm : X86Inst<"sete" , 0x94, MRMS0m, Arg8>, TB; // [mem8] = ==
def SETNEr : X86Inst<"setne", 0x95, MRMS0r, Arg8>, TB; // R8 = !=
def SETNEm : X86Inst<"setne", 0x95, MRMS0m, Arg8>, TB; // [mem8] = !=
def SETBEr : X86Inst<"setbe", 0x96, MRMS0r, Arg8>, TB; // R8 = <= unsign
def SETBEm : X86Inst<"setbe", 0x96, MRMS0m, Arg8>, TB; // [mem8] = <= unsign
def SETAr : X86Inst<"seta" , 0x97, MRMS0r, Arg8>, TB; // R8 = > signed
def SETAm : X86Inst<"seta" , 0x97, MRMS0m, Arg8>, TB; // [mem8] = > signed
def SETSr : X86Inst<"sets" , 0x98, MRMS0r, Arg8>, TB; // R8 = <sign bit>
def SETSm : X86Inst<"sets" , 0x98, MRMS0m, Arg8>, TB; // [mem8] = <sign bit>
def SETNSr : X86Inst<"setns", 0x99, MRMS0r, Arg8>, TB; // R8 = !<sign bit>
def SETNSm : X86Inst<"setns", 0x99, MRMS0m, Arg8>, TB; // [mem8] = !<sign bit>
def SETLr : X86Inst<"setl" , 0x9C, MRMS0r, Arg8>, TB; // R8 = < signed
def SETLm : X86Inst<"setl" , 0x9C, MRMS0m, Arg8>, TB; // [mem8] = < signed
def SETGEr : X86Inst<"setge", 0x9D, MRMS0r, Arg8>, TB; // R8 = >= signed
def SETGEm : X86Inst<"setge", 0x9D, MRMS0m, Arg8>, TB; // [mem8] = >= signed
def SETLEr : X86Inst<"setle", 0x9E, MRMS0r, Arg8>, TB; // R8 = <= signed
def SETLEm : X86Inst<"setle", 0x9E, MRMS0m, Arg8>, TB; // [mem8] = <= signed
def SETGr : X86Inst<"setg" , 0x9F, MRMS0r, Arg8>, TB; // R8 = < signed
def SETGm : X86Inst<"setg" , 0x9F, MRMS0m, Arg8>, TB; // [mem8] = < signed
// Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
// register allocated to cmovXX XY, Z

12
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -226,6 +226,18 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break;
case X86::SHRDrrCL32:NI = MakeMRInst( X86::SHRDmrCL32,FrameIndex, MI);break;
case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break;
case X86::SETBr: NI = MakeMInst( X86::SETBm, FrameIndex, MI); break;
case X86::SETAEr: NI = MakeMInst( X86::SETAEm, FrameIndex, MI); break;
case X86::SETEr: NI = MakeMInst( X86::SETEm, FrameIndex, MI); break;
case X86::SETNEr: NI = MakeMInst( X86::SETNEm, FrameIndex, MI); break;
case X86::SETBEr: NI = MakeMInst( X86::SETBEm, FrameIndex, MI); break;
case X86::SETAr: NI = MakeMInst( X86::SETAm, FrameIndex, MI); break;
case X86::SETSr: NI = MakeMInst( X86::SETSm, FrameIndex, MI); break;
case X86::SETNSr: NI = MakeMInst( X86::SETNSm, FrameIndex, MI); break;
case X86::SETLr: NI = MakeMInst( X86::SETLm, FrameIndex, MI); break;
case X86::SETGEr: NI = MakeMInst( X86::SETGEm, FrameIndex, MI); break;
case X86::SETLEr: NI = MakeMInst( X86::SETLEm, FrameIndex, MI); break;
case X86::SETGr: NI = MakeMInst( X86::SETGm, FrameIndex, MI); break;
case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 ,FrameIndex, MI); break;
case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16,FrameIndex, MI); break;
case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32,FrameIndex, MI); break;