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Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
This commit is contained in:
Owen Anderson
parent
09095b4dd9
commit
5aff471eb8
@ -127,7 +127,7 @@ def imm0_255_not : PatLeaf<(i32 imm), [{
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def t2addrmode_imm12 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
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let PrintMethod = "printAddrModeImm12Operand";
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string EncoderMethod = "getT2AddrModeImm12OpValue";
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string EncoderMethod = "getAddrModeImm12OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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@ -146,11 +146,6 @@ def t2am_imm8_offset : Operand<i32>,
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string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
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}
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def t2am_imm12_offset : Operand<i32> {
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string EncoderMethod = "getT2AddrModeImm12OffsetOpValue";
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}
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// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
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def t2addrmode_imm8s4 : Operand<i32> {
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let PrintMethod = "printT2AddrModeImm8s4Operand";
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@ -845,9 +840,10 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<16> addr;
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let Inst{19-16} = addr{15-12}; // Rn
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let Inst{11-0} = addr{11-0}; // imm
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bits<17> addr;
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{23} = addr{12}; // U
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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@ -925,9 +921,10 @@ multiclass T2I_st<bits<2> opcod, string opc,
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<16> addr;
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let Inst{19-16} = addr{15-12}; // Rn
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let Inst{11-0} = addr{11-0}; // imm
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bits<17> addr;
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{23} = addr{12}; // U
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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@ -1539,14 +1536,14 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
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[(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = instr;
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let Inst{23} = 1; // U = 1
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let Inst{22} = 0;
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let Inst{21} = write;
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let Inst{20} = 1;
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let Inst{15-12} = 0b1111;
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bits<16> addr;
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let Inst{19-16} = addr{15-12}; // Rn
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bits<17> addr;
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{23} = addr{12}; // U
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let Inst{11-0} = addr{11-0}; // imm12
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}
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@ -1584,24 +1581,6 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
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let Inst{3-0} = addr{5-2}; // Rm
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let Inst{5-4} = addr{1-0}; // imm2
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}
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let isCodeGenOnly = 1 in
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def pci : T2Ipc<(outs), (ins t2am_imm12_offset:$addr), IIC_Preload, opc,
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"\t$addr",
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[]> {
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let Inst{31-25} = 0b1111100;
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let Inst{24} = write;
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let Inst{23} = ?; // add = (U == 1)
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let Inst{22} = 0;
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let Inst{21} = instr;
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let Inst{20} = 1;
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let Inst{19-16} = 0b1111; // Rn = 0b1111
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let Inst{15-12} = 0b1111;
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bits<13> addr;
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let Inst{23} = addr{12};
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let Inst{11-0} = addr{11-0};
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}
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}
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defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
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@ -185,8 +185,6 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getSORegOpValue - Return an encoded so_reg shifted register value.
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unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
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@ -745,19 +743,6 @@ getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
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return Value;
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}
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unsigned ARMMCCodeEmitter::
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getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO1 = MI.getOperand(OpNum);
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const MCOperand &MO2 = MI.getOperand(OpNum+1);
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// FIXME: Needs fixup support.
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unsigned Value = getARMRegisterNumbering(MO1.getReg());
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Value <<= 12;
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Value |= MO2.getImm() & 4095;
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return Value;
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}
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unsigned ARMMCCodeEmitter::
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getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -350,36 +350,6 @@ static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) {
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return decodeThumbInstruction(insn);
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}
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static inline bool Thumb2PreloadOpcodeNoPCI(unsigned Opcode) {
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switch (Opcode) {
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default:
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return false;
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case ARM::t2PLDi12: case ARM::t2PLDi8:
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case ARM::t2PLDs:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWs:
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case ARM::t2PLIi12: case ARM::t2PLIi8:
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case ARM::t2PLIs:
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return true;
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}
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}
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static inline unsigned T2Morph2Preload2PCI(unsigned Opcode) {
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switch (Opcode) {
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default:
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return 0;
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case ARM::t2PLDi12: case ARM::t2PLDi8:
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case ARM::t2PLDs:
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return ARM::t2PLDpci;
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWs:
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return ARM::t2PLDWpci;
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case ARM::t2PLIi12: case ARM::t2PLIi8:
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case ARM::t2PLIs:
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return ARM::t2PLIpci;
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}
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}
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//
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// Public interface for the disassembler
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//
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@ -486,11 +456,6 @@ bool ThumbDisassembler::getInstruction(MCInst &MI,
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// instructions as well.
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unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
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// A8.6.117/119/120/121.
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// PLD/PLDW/PLI instructions with Rn==15 is transformed to the pci variant.
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if (Thumb2PreloadOpcodeNoPCI(Opcode) && slice(insn, 19, 16) == 15)
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Opcode = T2Morph2Preload2PCI(Opcode);
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ARMFormat Format = ARMFormats[Opcode];
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Size = IsThumb2 ? 4 : 2;
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@ -1711,11 +1711,11 @@ static inline bool Thumb2PreloadOpcode(unsigned Opcode) {
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switch (Opcode) {
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default:
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return false;
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case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDpci:
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case ARM::t2PLDi12: case ARM::t2PLDi8:
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case ARM::t2PLDs:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWpci:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWs:
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case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIpci:
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case ARM::t2PLIi12: case ARM::t2PLIi8:
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case ARM::t2PLIs:
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return true;
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}
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@ -1752,8 +1752,7 @@ static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
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&& !OpInfo[OpIdx].isOptionalDef()
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&& "Pure imm operand expected");
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int Offset = 0;
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if (Opcode == ARM::t2PLDpci || Opcode == ARM::t2PLDWpci ||
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Opcode == ARM::t2PLIpci) {
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if (slice(insn, 19, 16) == 0xFF) {
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bool Negative = slice(insn, 23, 23) == 0;
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unsigned Imm12 = getImm12(insn);
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Offset = Negative ? -1 - Imm12 : 1 * Imm12;
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@ -614,7 +614,6 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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MISC("it_mask", "kOperandTypeThumbITMask"); // I
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MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
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MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
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MISC("t2am_imm12_offset", "kOperandTypeThumb2AddrModeImm12Offset");//I
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MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
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MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
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MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
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@ -841,7 +840,6 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
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operandTypes.addEntry("kOperandTypeThumb2SoImm");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12Offset");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
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operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
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