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AMDGPU/SI: Fix commuting of 32-bit VOPC instructions

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Summary:
We didn't have entries in the commuting table for the 32-bit
instructions.  I don't think we hit this problem now, but we
will once uniform branching is enabled.  Tests will come in
a later commit.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16600

llvm-svn: 258936
This commit is contained in:
Tom Stellard 2016-01-27 15:53:52 +00:00
parent 730e8cf8fe
commit 5b34ccce2a
1 changed files with 4 additions and 2 deletions
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6
lib/Target/AMDGPU/SIInstrInfo.td
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@ -1788,7 +1788,8 @@ multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
list<SchedReadWrite> sched,
string revOpName = "", string asm = opName#"_e32 "#op_asm,
string alias_asm = opName#" "#op_asm> {
def "" : VOPC_Pseudo <ins, pattern, opName> {
def "" : VOPC_Pseudo <ins, pattern, opName>,
VOP2_REV<revOpName#"_e32", !eq(revOpName, opName)> {
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let SchedRW = sched;
}
@ -1819,7 +1820,8 @@ multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
list<dag> pat64, bit DefExec, string revOp,
VOPProfile p, list<SchedReadWrite> sched> {
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched,
revOp>;
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
opName, p.HasModifiers, DefExec, revOp, sched>;