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Patterns to match AVX 256-bit vzero intrinsics

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llvm-svn: 110480
This commit is contained in:
Bruno Cardoso Lopes 2010-08-06 22:10:01 +00:00
parent 13c66ce161
commit 5b602f8822
2 changed files with 6 additions and 6 deletions
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4
include/llvm/IntrinsicsX86.td
View File

@ -1272,9 +1272,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Vector zero
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">,
Intrinsic<[], [], [IntrNoMem]>;
Intrinsic<[], [], []>;
def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">,
Intrinsic<[], [], [IntrNoMem]>;
Intrinsic<[], [], []>;
}
// Vector load with broadcast

8
lib/Target/X86/X86InstrSSE.td
View File

@ -5408,12 +5408,12 @@ def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
[]>, VEX_4V;
// Zero All YMM registers
def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L,
Requires<[HasAVX]>;
def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
[(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
// Zero Upper bits of YMM registers
def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX,
Requires<[HasAVX]>;
def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
[(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
} // isAsmParserOnly